特長
- 14-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- 50% more dynamic driver strength than standard SSTU32864
- Supports LVCMOS switching levels on C1 and RESET# inputs
- Low voltage operation
説明
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.
適用されたフィルター
読込中