概要
説明
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for non parity DDR2 RDIMMs for 400 and 533MHz.
特長
- 1:1 and 1:2 registered buffer
- 1.8V Operation
- SSTL_18 style clock and data inputs
- Differential CLK input
- Control inputs compatible with LVCMOS levels
- Flow-through architecture for optimum PCB design
- Latch-up performance exceeds 100mA
- ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
- Maximum operating frequency: 340MHz
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