特長
- 3V to 3.6V operating voltage
- 48MHz to 160MHz output frequency range
- Input from fundamental crystal oscillator or external source
- Internal PLL feedback (loading the feedback output relative to the other outputs, will adjust the propagation delay between REF inputs and outputs)
- Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8)
- Low jitter
- PLL bypass for testing and power-down control (S1 = H, S0 = H, powers part down <500?A)
- Available in TSSOP package
5V926A - Block Diagram
説明
The IDT5V926A is a low-cost, low skew, low jitter, and high-performance clock multiplier with a reference clock from either a lower frequency crystal or clock input. It has been specially designed to interface with Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz clock from 25MHz input. It can be programmed to provide output frequencies ranging from 48MHz to 160MHz, with input frequencies ranging from 6MHz to 80MHz. The IDT5V926A includes an internal RC filter that provides excellent jitter characteristics and eliminates the need for external components. When using the optional crystal input, the device accepts a 10 - 40MHz fundamental mode crystal with a maximum equivalent series resistance of 50?.
