5T9110

The 5T9110 is a 2.5V PLL differential clock driver intended for high-performance computing and data communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T9110 has six differential programmable skew outputs in six banks, including a dedicated differential feedback. Skew is controlled by 3-level input signals that may be hardwired to appropriate high-mid-low levels. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from 1 to 12 using the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or 4. The 5T9110 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. The selectable interface is controlled by 3-level input signals that may be hardwired to appropriate high-mid-low levels. The differential outputs can be synchronously enabled/disabled. Additionally, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.