Renesas' leading RF clock and JESD204B clock portfolio consists of devices designed for exceptional jitter performance (lowest phase noise). The RF-PLL-based clock devices support RF frequency generation, jitter attenuation, as well as frequency and phase manipulation. RF buffers with very low additive phase noise complement the RF-PLL clock generators with signal fanout functions. RF dividers perform frequency conversion. Specific RF clock devices are optimized for JESD204B standard. Output signalling levels supported by the RF buffers, RF dividers, RF-PLL oscillators devices as well as JESD204B clocks include LVPECL and LVDS.
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Industry-leading RF Clock Synthesizers and RF PLLs
Renesas offers high-performance RF clock synthesizers and RF PLLs for conditioning and frequency/phase management compliant to JESD204B, supporting JESD204B subclass 0 and 1 clock implementations.
The RF clock solutions are optimized to deliver excellent phase noise performance and are very flexible in programming of the output frequency and phase. A dual-stage RF PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL uses an external VCXO for best possible noise characteristics.
The RF PLLs generate the necessary high-frequency clocks and low-frequency system reference signals (SYSREF) where the system reference signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. Multiple clock inputs are available for redundancy purpose and all inputs are monitored for activity. Priority-controlled auto-switching, manual switchover and hold-over are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency RF dividers and phase adjustment capabilities are added for flexibility.
JESD204B Clock Fanout Buffers (RF Buffer)
Renesas is proud to offer the world’s first RF buffers supporting high-speed JESD204B clocking. The RF buffers feature configurable phase delay and extremely low additive phase noise, offering maximum design flexibility and performance. Supporting frequencies up to 1228.8 MHz, Renesas' RF buffers support the latest generation of high-speed JESD204B analog-to-digital (ADC) and digital-to-analog (DAC) data converters, delivering high-quality clock signals to improve overall base station signal quality and increase data throughput via lower system bit error rates (BER). Furthermore, base-station developers may reduce system costs by simplifying filters as a result of less noise in the signal path.
Renesas' leading RF buffers use silicon-germanium (SiGe) technology to support the distribution of high-frequency clocks and system reference signals with low additive phase noise and high-power supply noise rejection. The clock outputs are configurable for both amplitude and phase delay for flexibility in achieving radio board synchronization as well as fine-tuning the system for optimal performance. In addition, Renesas' RF buffers offer configurable power-down control, enabling sophisticated power-saving schemes for improved system efficiency.
About JESD204B Clocks (RF Clocks)
JESD204B clocks are used in systems that implement the JESD204B high-speed serial interface. Now in its third iteration, the JESD204B standard defines a maximum lane rate up to 12.5 Gbps per channel, with support for harmonic frame clocking and deterministic latency. In previous versions of JESD204, the frame clock was the absolute timing reference in the system. Typically, both the frame clock and the data converter sampling clock were the same, which limited the flexibility of the system and made multi-device synchronization very complex. In JESD204B, the device clock is the timing reference for each device in the system. The Renesas JESD204B clock generators (RF clocks) provide a high-quality source for these timing signals, resulting in exceptional system performance and reliability.