Overview

The 8V19N850 is a fully integrated Radio Unit Clock Synchronizer and Jitter Attenuator designed as a high-performance clock solution for phase/frequency synchronization and signal conditioning of wireless base station radio equipment. The device supports JESD204B/C subclass 0 and 1 device clocks and SYSREF synchronization for converters. The 8V19N850 supports two independent frequency domains: one that can be used for the digital clock (Ethernet and FEC rates) domain with four outputs, and the device clock (RF-PLL) domain with 12 outputs. The Ethernet domain generates frequencies from two independent APLLs for flexibility; the outputs of the RF clock domain generate very low phase noise clocks for ADC/DAC circuits.

From the integrated RF-PLL, the device supports the clock generation of high-frequency device clocks for driving ADC/DAC devices low-frequency synchronization signals (SYSREF). A dual DPLL front-end architecture supports any frequency translation. Each DPLL provides a programmable bandwidth and a DCO function for real-time frequency/phase adjustments. The DPLLs can lock on 1PPS input signals and establish lock within 100s or less. Frequency information can be applied from DPLL-0 to DPLL-1 and vice versa to enable the combining of the frequency characteristics of two references (combo-mode). The 8V19N850 is configured through a pin-mapped I3C (including legacy I2C) and 3/4-wire SPI interface. I2C with master capabilities reads a default configuration from an external ROM device. GPIO ports can be configured for reporting and controlling purposes.

  • Device clock domain (RF-PLL) with support for JESD204B/C
  • Digital clock domain (Ethernet, FEC) with support for eEEC and T-BC/T-TSC Class C
  • 2 differential clock reference inputs with 1PPS (1Hz) to 1GHz input frequency
  • Dual DPLL front-end with independent clock paths
    • External control of the DCO for IEEE1588
    • Digital holdover with a 1.1 × 10-7 ppb accuracy
    • Programmable DPLL loop bandwidth 1mHz - 6kHz
    • Configurable phase delay (range: 1UI)
    • Hitless input switching with < 1ns output phase error
  • Reference monitors for input LOS, activity and frequency
  • 1 external synchronization input for JESD204B/C (LVCMOS)
  • 16 differential outputs
  • Optimized for low phase noise: -146dBc/Hz (1MHz offset; 245.76MHz clock)
  • Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
  • Board temperature range: -40°C to +105°C
  • Applicable Standards
    • ITU-T G.8262 EEC1/2, G.8262.1 eEEC
    • ITU-T G.8273.2 T-BC/T-TSC Class C
    • JESD204B and C
  • Wireless infrastructure 5G radio

Documentation

Title Type Date
PDF1.77 MB
Datasheet
PDF1.99 MB
Application Note
PDF261 KB
Application Note
PDF41 KB
Application Note
PDF148 KB
Application Note
PDF495 KB
Application Note
PDF115 KB
Application Note
PDF233 KB
Application Note
PDF565 KB
Application Note
PDF121 KB
Application Note
PDF438 KB
Application Note
PDF401 KB
Guide
PDF2.66 MB
Manual - Development Tools
PDF331 KB
Overview
PDF1.83 MB
Overview
PDF2.55 MB
Report
PDF400 KB
White Paper

Design & Development

Software Downloads

Title Type Date
TCP5.31 MB
Software & Tools - Other

Boards & Kits

Models

Title Type Date
ZIP35 KB
Model - IBIS

Videos & Training

Demystifying 5G Video Series

Rohde & Schwarz's Demystifying 5G video series discusses main topics related to 5G including new technology components, procedures and testing challenges.

Watch Now

8V19N850 5G Radio Synchronizer

This video introduces the industry’s first fully-integrated synchronizer for 5G enhanced common public radio interface (eCPRI) radio synchronization.