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9ZXL0451E

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4-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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Features

  • LP-HCSL outputs eliminate 16 resistors; save 32mm2 of area
  • PCIe Gen 1–5 compliance
  • 4 OE# pins; SMBus control also available
  • 3 selectable SMBus addresses
  • 2 selectable ZDB bandwidths; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of ZDB bandwidth and fanout modes
  • Spread spectrum compatible
  • 100MHz ZDB mode
  • 5mm × 5mm 32-VFQFPN package; small board footprint
Find Other Products in Processor Clock Buffers
9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0451E - Pinout
9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0451E - Pinout

Description

The 9ZXL0451E is a second-generation enhanced performance DB800ZL derivative for PCIe Gen 4 and 5 applications. In fanout (bypass) mode, it is DB2000Q compatible. A fixed external feedback in zero-delay buffers (ZDB) mode maintains low drift for critical QPI/UPI.

Parameters

Attributes Value
Chipset Manufacturer Intel
Clock Spec. DB800ZL v1.2 Derivative
Diff. Outputs 4
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 4
Output Freq Range (MHz) 1 - 400
Diff. Inputs 1
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 158
Advanced Features Multiple SMBus addresses, SW PLL mode control
App Jitter Compliance 25G EDR, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, DB2000Q, QPI, UPI
Package Area (mm²) 81

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 5.0 x 5.0 x 0.9 32 0.5

Applications

  • Servers/High-performance computing
  • nVME storage
  • Networking
  • Accelerators
  • Industrial control

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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