Name: 5P49V5923 - VersaClock 5 Low Power Programmable Clock Generator
Brand: Renesas Electronics Corporation
SKU: 5P49V5923 - VersaClock 5 Low Power Programmable Clock Generator
Availability: OutOfStock

Features

3 LVCMOS outputs, including 1 reference output
In-system programmable with 2 independent output frequencies
Up to 200 MHz input/output frequencies
Also supports crystal input
Stores 4 different configurations in OTP non-volatile memory
< 100 mW core power (at 3.3V)
< 0.7 ps RMS phase jitter (typ)
Meets PCIe® Gen1/2/3, USB 3.0, 1/10 GbE clock requirements
1.8 / 2.5 / 3.3V core and output voltages
4x4 mm 24-ld VFQFPN
-40° to +85°C operating temperature range
Supported by Timing Commander™ software tool

Find Other Products in Programmable Clocks

Description

The 5P49V5923 is low-power programmable clock generator with best-in-class jitter performance and design flexibility with LVCMOS outputs capable of generating any output frequency. The 5P49V5923 is intended for high performance consumer, networking, industrial, computing, and data-communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock^® 5). The frequencies are generated from a single reference clock or crystal input. A glitchless manual switchover function allows one of the redundant clock inputs to be selected during normal operation.

Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or system production margin testing. The device may be configured to use one of two I²C addresses to allow multiple devices to be used in a system.

Parameters

Attributes	Value
App Jitter Compliance	PCIe Gen1, PCIe Gen2, PCIe Gen3
Outputs (#)	3
Output Type	LVCMOS
Output Freq Range (MHz)	-
Input Freq (MHz)	-
Inputs (#)	2
Input Type	Crystal, LVCMOS, LVPECL, LVDS, HCSL
Output Banks (#)	2
Core Voltage (V)	1.8, 2.5, 3.3
Output Voltage (V)	1.8, 2.5, 3.3
Phase Jitter Typ RMS (ps)	0.7
Prog. Interface	I2C, OTP
Spread Spectrum	Yes

Package Options

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
VFQFPN	4.0 x 4.0 x 0.9	24	0.5

Applied Filters:

Filters

Description

This video provides an overview of the VersaClock 5 programmable clock generator family, including the 5P49V5901, 5P49V5913, 5P49V5914, 5P49V5923, 5P49V5925, 5P49V5927, 5P49V5929.

The VersaClock 5 family is an in-system programmable clock generator featuring up to four universal output pairs capable of producing independent frequencies up to 350 MHz configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill-of-materials. Upon request, devices may be factory-programmed to the customer’s desired configuration.

Presented by Baljit Chandhoke, product line manager at IDT. Visit the Programmable Clocks page for more information.

Transcript

Hello. My name is Baljit Chandhoke, and I'm the Product Line Manager of Timing Products at IDT. Today I'll give you a brief presentation of our recently released VersaClock® 5 family of programmable clock generators.

VersaClock 5 is an extremely low-power field programmable clock generator which can generate any output frequency you would like up to 350 megahertz, with best in class jitter performance of 0.7 ps RMS phase jitter.

This slide shows you the block diagram of VersaClock 5 family. As you see in the block diagram, there are four fractional output dividers which can generate any output frequency you want. These are connected to four universal outputs. The universal outputs can be configured as LVPECL, LVDS, HCSL, or two LVCMOS outputs per output pair. In addition, there is a reference clock output as well. For the inputs you can have a crystal input, or a clock input which is selectable by clock select. With the crystal input, the device acts as a clock generator. With the clock input the device acts as a clock multiplier. Each of the outputs can be configured to be 1.8 volt, 2.5 volt, or 3.3 volt outputs. As you see, the device is very programmable with a lot of flexibility. There are three options of programming the device. The device can be programmed using I2C, in which case every time at power-up you will need to reprogram the device. The second option is there are four banks of one-time programmable memory which enable you to program the configuration in the device. This can be done in-system, and next time the device powers up, it can power up to your desired configuration. The four configurations can be selected using cell zero and cell one pins. The third option is factory programming in which IDT will program the device to your configuration so no programming is required by the customer.

So to summarize, VersaClock 5 family of products have extremely low current consumption with 30 mA versus 60 mA from the competitor. There are four universal outputs which can be configured as HCSL, LVPECL, LVDS, or two LVCMOS outputs. And the device is in-system field programmable, and you can do the free programming using I2C or Timing Commander software from IDT.

This is a performance of the VersaClock 5 family. The RMS phase jitter is 610 fsecs from 12KHz to 20 MHz as you see on the slide. The device from the VersaClock 5 family are compliant PCI express Gen 1, Gen 2, Gen 3. They're compliant to 1G Ethernet. They're compliant to 10 G Ethernet. They're compliant to USB 3.0 Thunderbolt standards.

This slide summarizes the seven devices that we have in production for the VersaClock 5 family. The flagship device, 5P49V5901, has four fractional output dividers and can generate any output frequency you want, up to 350 MHz. The outputs can be configured to be LVPECL, LVDS, HCSL, or LVCMOS output, plus a reference output. The 5P49V5913 has two fractional output dividers so this is for applications which need less number of outputs. The 5P49V5913 can be used for applications which need three universal outputs. 5P49V5914 can be used. The other four devices are devices which only have LVCMOS outputs. So depending upon your application, if you need three, five, seven, or nine LVCMOS outputs, one of these devices can be selected.

This slide shows you the block diagram for two universal output devices. These devices have a reduced number of outputs with the same flexibility, programmability, performance as our flagship device, and it enables our customers to get the exact functionality they need on their systems in the most cost-effective manner.

This slide shows you the block diagram of 5P49V5923. This device only has LVCMOS outputs. And with the four devices as mentioned on the slide, having reduced functionality of only having LVCMOS outputs, they are extremely cost-competitive and these devices can be used to replace LVCMOS crystal oscillators.

This slide shows you the nine outputs to LVCMOS output device.

As I mentioned earlier, all the programming for the VersaClock 5 family can be done using the Timing Commander graphical user interface. It's extremely easy to use. And with the Timing Commander, you can program the output types. You can program the frequencies. And you can even program the Spread Spectrum independently on each output.

The VersaClock 5 family of devices are all in 4 x 4 mm QFN 24-pin package. They have the same footprint and are compatible with each other.

Some of the typical applications for the VersaClock 5 family are high-end consumer, networking, computing, industrial, communications, broadcast video, and medical applications.

For the VersaClock 5 we've also given our customers a web tool which enables them to get pre-programmed samples of VersaClock 5. So if you go to the VersaClock 5 IDT homepage and click on the customized link, you will get a utility like this. With this utility you will be able to enter the input frequency, enter the output frequency, output type, and instantaneously you will get a part number, and a data sheet addendum, and the ability to request samples with your configuration.

So this is how the data sheet addendum looks like. It shows you your configuration.

The VersaClock 5 family also has a programmer board available which in stock at IDT and ships within 24 hours of placing an order. The part number for the board is shown on the slide.

There are five evaluation boards for the VersaClock 5 family and they also are all available to ship within 24 hours of placing an order. The part numbers are shown on the slide.

All the collateral for VersaClock 5 family is on IDT.com as you see on the slide. So we have the evaluation board user's guide. We have the data sheets. We have the IBIS models, the Timing Commander personality file, reference schematics, and the product video all can be seen on IDT.com.

In summary, IDT's VersaClock 5 family of devices is an extremely low-power, programmable clock generator with best in class performance and design flexibility. It's got excellent jitter performance with 0.7 ps RMS phase jitter. We have reduced functionality devices with 5913 and 5914 which only have two or three universal outputs, enabling customers to get the exact functionality that they need in the systems in the most cost-effective manner. Then we have only LVCMOS output devices which are extremely low-cost to go after replacing LVCMOS crystal oscillators. These devices consume extremely low current consumption with 30 mA core current and they are compliant to PCI Express Gen 1, Gen 2, Gen 3. They're compliant to 1G Ethernet, 10 G Ethernet. IDT's VersaClock 5 family provides the industry's most versatile clock generation solution for consumer, industrial, communications, and networking applications.

Thank you for your time.

Description:

Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer shows phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information visit the Programmable Clocks page.

Transcript:

Hello, my name is Baljit Chandhoke, and I'm the Product Line Manager of timing products at IDT. Today, I will be giving you a brief lab demonstration of our new product, "VersaClock 5".

VersaClock 5 is a low power clock generator, with best-in-class jitter performance of 0.7 psec. It has extremely low power with core current consumption of only 30 MA. It is extremely programmable, and you can get any frequency you want at the output, up to 350MHz.

Now I'm going to start the lab demonstration. I have with me, an evaluation board. The evaluation board is powered by the USB cable, and is also used to control the VersaClock 5.

This is the Timing Commander software, which controls the VersaClock 5 device. As you see, I have it configured for 125MHz, LVPECL output, on Output 1.

On Output 2, I have it configured at 125MHz, HCSL output. Output 3, I have it configured at 156.25MHz LVDS, and Output 4 has 312.5MHz. All the outputs are operational and have different output frequencies.

Now, let's take a look at the performance. With all these outputs operational, and on Output 1, which is operating at 125MHz, I see 575 fsec RMS phase jitter from 12K to 20MHz.

This is industry leading in the power consumption of 30MA core in the space.

Now let's change the frequency and see what happens to the phase noise. I'm going to change the frequency on Output 1 to 100MHz.

As you see, the frequency changed to 100MHz as shown on the screen, and the phase noise is still 576 fsec, from 12K to 20MHz. The noise floor is close to 150dBc.

So this product maintains the great performance, across a wide range of frequencies, as well as across multiple output types, and with different frequencies of the output.

So it provides you, a complete system solution, meeting the requirements of all your clocking needs in your system.

Description

VersaClock® 5 is a low-power programmable clock generator with best-in-class jitter performance with less than 0.7psec RMS phase jitter from 12KHz to 20MHz. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill-of-materials. The high-performance clock generator operates at less than 100mW core power (50 percent lower than competing devices), helping to ease system thermal constraints and reduce operating power expenses.

VersaClock 5 can take a crystal or a clock input. It has 4 fractional output dividers which allow the programming of 4 independent frequencies up to 350MHz. The four universal output pairs are independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. It also features a reference clock output. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about Renesas's VersaClock programmable clock generators, visit our page.

Transcript

Hello, my name is Baljit Chandhoke and I’m the Product Marketing Manager of Timing Products at IDT. Today, I will give you a brief introduction of our new low power programmable clock family, VersaClock 5.

VersaClock 5 is a low power, programmable clock generator with best in class jitter performance with less than .7ps RMS phase jitter from 12KHZ to 20MHz. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill of materials. It also has a buffered reference clock output.

The high performance clock generator operates at less than 100mW core power, 50% lower than competing devices, with typical total device power of 300mW with all outputs operational, helping to ease system tunnel constraints and reduce operating power expenses. VersaClock 5 has four universal output pairs. Each output pair can be configured as HCSL, LVPECL, LVDS, or two LVCMOS outputs. VersaClock 5 has in-system, programmable clock generator via I2C as well as IDT’s Timing Commander Software.

This slide shows the block diagram of VersaClock 5. VersaClock 5 can take a crystal or clock input. It has four fractional output dividers, which allow programming of four independent frequencies, up to 350MHz. The four universal output pairs are independently configurable as HCSL, LVPECL, LVDS or dual LVCS outputs. It also features a reference clock output. The fractional output dividers driving each output pair are easily programmed via I2C, while the device is operating in the system, enabling system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project imagery consolidation or design changes in field. Upon request, the devices may be factory programmed to customer’s desired configuration.

VersaClock 5 has excellent phase jitter performance with 610fsec RMS phase jitter, as shown on the phase noise plot. With RMS phase jitter less than .7ps or the full 12KHz to 20MHz integration range, the new device meets the stringent jitter requirements of PCI Express Gen 1, Gen 2, and Gen 3, as well as USB3.0 and 1G/10G Ethernet.

IDT’s new Timing Commander Software platform enables customers to configure program VersaClock 5 with an intuitive and flexible graphical user interface, as you see on the slide. You can program the four fractional output dividers, providing four independent output frequencies with 0 ppm error. You can configure universal output pairs as differential LVDs, HCSL, LVPECL, or two single unit outputs, as well as program each output independently with spread spectrum, if needed.

VersaClock 5 is useful in high-end consumer applications, networking applications, computing applications, industrial communications, broadcast radio and medical applications.

The block diagram shows a typical application of VersaClock 5, which has a 125 LVPECL output for gigabit Ethernet, a 156.25MHz LVDS output for 10 gig Ethernet and a 100MHz HCSL output for PCIe Gen3, as well as a 25MHz reference output. With all the different outputs operational and the cross-talk – including the cross-talk, we get 700fsec integrated phase jitter from 12KHz to 20MHz. The key application issues solved by VersaClock 5 are shown on the slide.

In summary, VersaClock 5 is a low-power, programmable clock generator with best-in-class performance and design flexibility. It has excellent phase jitter performance. Our wide range of frequencies provides design flexibility with less than .7ps RMS phase jitter from 12KHz to 20MHz. VersaClock 5 has significantly less power consumption, which enables easing thermal constraints in the system. IDT VersaClock 5 programmable clocks are ideal clocking solutions for a wide range of applications replacing crystal oscillators, clock generators – allowing for in-system programming, saving BOM and board space, as well as improving time to market and shortening design time. IDT VersaClock 5 provides industry’s most versatile, low-power clock generation solution for consumer, computing, industrial, communications and networking applications.

We have complete product support for VersaClock 5. We have a product brief, product data sheet, programming guide, elevation board with user’s manual, Timing Commander Software with user’s manual, product radio reference schematic available at the link shown on the slide.

Thank you for your time.

Description

This is a video introduction and demonstration of the VersaClock 5 Evaluation Board. This device uses Renesas's Timing Commander™ software platform, allowing engineers to configure and program their devices with an intuitive, time-saving graphical user interface (GUI).

The 5P49V5901 is an in-system programmable clock generator featuring four universal output pairs capable of producing independent frequencies up to 350 MHz in various output types. With RMS phase jitter less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range, the new device meets the stringent jitter requirements of PCI Express® Gen 1/2/3, USB 3.0, and 1G/10G Ethernet. The high-performance clock generator operates at less than 100 mW core power (50 percent lower than competing devices), helping to ease system thermal constraints, reduce operating power expenses, and maximize battery life.

The 5P49V5901's four universal output pairs are each independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Shudong Zheng, Sr. Design Engineer at IDT. For more information about Renesas's VersaClock 5, visit our VersaClock5 page.

Transcript

Hi, my name is Shudong Zhen. I'm the application engineer in IDT timing group. Today, I'm going to introduce you to the VersaClock 5 Evaluation Board. The board comes in a box, a full package. First of all, of course, this board is out of the static bag.

This is the board with the USB cable. So, this is the board. It has two power systems. As you can see, there are two red banana jacks and one black banana jack for the power return. Also, we support the USB power for the whole board.

For this demonstration, I'm going to use the USB power because this is the first power supply we recommend you to use. It's easy. You don't need to connect the cables to the bench power supply.

Now here, we have the VersaClock 5 timing commander GUI opened up in a computer and right now, the board is not connected to the software. So, you can see there's no sign of communication between the software and the board. Now, let's make a connection to the board. The USB cable that comes with the box and one side, plug into the USB connector of the PC and then the other side goes to the board, the mini USB connector.

Now, up until this point, we're still not seeing the connection because we need to click on this chips symbol sign to make the connection but before I do that, I want to show you the default frequency output from the board.

Now, here is the scope, with the SMA connector cables. I'm going to connect these to the output one of the board. As you can see, on the scope screen, there is already 100 MHz LVCMOS differential output already, as you can see. So, this is the default output from the chip, output one and one B. As you can see, if I disconnect the power, there's no output and then when I connect to the power, the output is coming out right away. That's the default output.

Now, on this very same output, if I, in the VersaClock 5 Timing Commander GUI, if I change that output to 125 MHz, you're going to see the frequency change. Right now, this is the point I need to make the connection to the board so that the configuration can be downloaded into the chip.

So, first of all, click on the chip sign and then, as you can see, this area becomes green, which is a sign of successful connection to the board. Now, on the right side of this sign, if you hover the mouse onto the sign, you can see write all registers to the chip. Right now, I have 25 megaHertz crystal input. I entered 25 into the input frequency box and then, on the output frequency box for output one, I have entered 125 MHz.

Now, once I write this configuration into the chip, you're going to see the change on the screen, on the scope screen. Now, the GUI shows WriteAll has completed. The scope screen should have shown the 125 MHz output from the default 100 MHz. So, the configuration of the board is very easy once we have a good connection. The desired output frequency can be immediately displayed.

We can also use the bench power supply to power the board. These two red banana jacks and the one black banana jack are for the bench power supply. If we use this cable from the bench power supply to make the connection... So, this is a green cable but still, we use it as a power supply, 3.3 volts and this is for the return, the power return. At the same time, the USB cable can still be connected for the data communication. The power supply is provided by the connectors, although we need to make the jumpers. We know the jumpers will make the selections between the USB power and the jack power. In this case, for example, as you can see, the labels on this connector, the VDDD_J means the power is coming from the jack. So, we need to move the connector into the left side and it's the same move for all the other jumpers, to make the power supply switch. That's for the power supply and then I think that concludes the introduction to the VersaClock 5 Evaluation Board. Thank you very much for you time to listen to this video. Thank you.

Description

IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page .

Transcript

Narrator: In a data driven world, timing is everything. That's why more and more system design engineers are using products from the world leader in silicon timing, IDT. IDT has earned its reputation for excellence by providing a wide range of leading technologies for wireless and wired communications infrastructure, high performance computing, and advanced power management.

And with a product portfolio 10 times greater than the competition, IDT is uniquely qualified to be your one-stop-shop for timing solutions. IDT's innovative Windows-based software platform, Timing Commander, makes it easy to configure, program, and monitor all your sophisticated timing devices.

Steven: What's great about IDT's Timing Commander is that it helps you avoid tedious manageable configurations so you can focus on other areas of your design.

Narrator: IDT's Timing Commander serves up intuitive configuration interfaces or personalities for all of IDT's programmable timing products. With a few simple clicks, you can generate a comprehensive, interactive block diagram and modified desired input values, output values, and other configuration settings. The software also writes your settings over USB to an IDT evaluation board for immediate application in the circuit. It really is as easy as one, two, three.

Steven: The Timing Commander software automatically makes calculations, monitors status, and prepares register settings so you don't have to reference a data sheet. Built-in documentation is readily available. Just hover over a setting, and real time validation ensures that the configuration complies with data sheet specifications. Whether you're a first time user or an experienced engineer, Timing Commander offers you the right amount of control.

Narrator: To help you program complex devices more intuitively, Timing Commander's advanced features include the ability to create phase noise estimates, generate the schematic symbol and termination circuit and determine the optimal balance between performance and power consumption.

Steven: Once your devices are configured and tuned for optimal system performance, you can save the configuration files for factory-level programming prior to shipment.

Narrator: Timing Commander is just one example of the innovative timing solutions IDT delivers.

Peter: From simple fanout buffers and multiplexers to fully featured products like universal frequency translators, network synchronization devices, and VersaClock families, IDT has a wide range of products optimized for specific applications. You can also count on IDT for the lowest jitter and lowest power features to help you build the world class products your customers demand.

Narrator: It's time to put IDT timing solutions to work for your business, and with the power of Timing Commander software, it's easier than ever. To learn more, visit IDT online or give us a call today.

Description

IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming prior to shipment. Presented by Steven Gutierrez, Senior Product Application Engineer at IDT. For more information, visit our Timing Commander page.

Transcript

Hi, I'm Stephen Gutierrez, and over the course of the next few minutes, I will be sharing with you some of the features of Timing Commander, the new support tool for I.D.T. timing products.

Timing commander can support a single device or a family of devices from a single file. Currently, we are viewing a family of devices from the U.F.T. product line, and for this demo, we will be using the IDT-8T49N-283 device.

Timing Commander provides complete documentation that allows users to understand the function of each setting without having to consult the data sheet. As the user hovers over an element via a specific setting or a functional block, a tool tip containing detailed information appears. Many of the I.D.T timing products are complex, highly configurable devices. Timing Commander simplifies this configuration process by making the commonly used settings available at the top level.

In this case, all the user has to enter are the input frequencies and the output frequencies. As you have just noticed, the built-in optimization algorithm has configured the device on the fly, updating the functional blocks and the diagram with each of my inputs. Aside from providing information about valid settings, Timing Commander also validates the user inputs to ensure that they remain within the data sheet's specifications.

Here I have entered an invalid setting, and Timing Commander displays an error message plus a link that will direct me to the location of that error. Once corrected, the error message goes away. For users that want to access more detailed settings, Timing Commander provides a search tool that will help them quickly locate the settings.

For example, when searching for gain, Timing Commander will highlight the functional blocks and the setting that match the search term. In addition to the diagram view, Timing Commander also provides a bit-set view and a register view. The bit-set view displays the device settings with descriptive names and detailed information. The user can click on a bit-set to view more details or also search for a term. In addition to the bit-set view, the register view will allow a user to change individual settings.

The nice feature is that changes made in the bit-set view or register view will reflect back on the block diagram. In certain product families, Timing Commander offers additional tools and features, such as schematic symbols, termination guidelines, power calculations, and configuration specific phase noise simulations.

Timing Commander is an all-in-one resource for device information containing information from data sheets, modeling software, and simulation tools. Timing Commander and all supporting materials are available on IDT.com/go/TimingCommander.

IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

So, hi there, this is Ron Wade again and we're going to be talking about timing solutions that IDT has for NXP's QorIQ and Layerscape CPU. And in the middle here, what I've drawn, in the middle of the box here, is what I refer to as our all-in-one solutions. These are single chips that may have all the clocks you need to build your system around the NXP CPUs. So, the three parts I have listed here are the 6P49V205, the 5P49V5907, and 5P49V5908. These provide a mix of the clocks that were needed over here for the CPU cores and SerDes clocks, and they're all on a single chip. If these suit your needs, these are ideal, these are the smallest core footprint parts to use.

The other approach besides all-in-one is the building block approach, and I'm going to start over here on the left side with the CPU clocks and the memory controller. For this solution over here, we have the 5P49V5901, or it could be a 6901, depending on your requirements. And, this guy has the most flexibility as far as programming up any combination of DDR clock or CPU clock that you want, as well as the 24 MHz USB clock and a 125 MHz clock.

If you're using the Layerscape CPU with the reduced oscillator mode where you have the 100 MHz non-spread clock coming in, you might want to consider the 9FGV0 series or the 9FGL0 series. These are very high-performance PCI Express clock generators, the V being a 1.8 volt part and the L being a 3.3 volt part that are available. The terminations are integrated, they're very low power and they also have some extra copies in case SerDes is a PCI Express SerDes. So, this is the ideal solution if you want to go building block over here.

And then for the SerDes clocks, we've got the 125 MHz differential for Gigabit Ethernet, the 156 MHz for 10 gig, and the 100 MHz for PCIe. We have again a different set of flavors we can go with. We have the 5P49V6901, which is a better performing, lower phase jitter version of the 5901 over here. This guy's ideal if you have a mix of these SerDes frequencies in your design. If you're in a homogeneous environment, for instance, where everything's PCI Express or everything is 125 MHz, then you could use the 9FGV parts, or I'll use an output from over there, over on this side for the 100 MHz output, or you could use these guys programmed up to be 125 as well. Or if you've got a 125 coming from over there, you can use one of the 9DVD buffers which are the 1.8V buffers to fan that out. Likewise, we have similar parts with 3.3-volt power supplies, if that's what you prefer. The 9FGL0 series, it should give you the 100 to the 125, and the 9DVL0 series which can provide a fanout buffer for any of these three frequencies.

So, that's an overview of the timing solutions for NXP's QorIQ and Layerscape CPUs. This is Ron Wade at IDT again. Thanks for watching and see you next time.

IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

Hi there, this is Ron Wade with IDT and today we're going to talk about NXP, formerly known as Freescale, CPUs. Specifically the QorIQ and Layerscape CPUs and the timing requirements that they have. So, it's basically divided into a couple of parts here. There's some timing that the CPU itself requires and then there's timing that depends upon your system and the number of SerDes links you have in your design and in your CPU. So, if we talk about the CPU part itself, we have the CPU cores which get a clock, and we have the memory controller inside the CPUs which gets a clock as well. And the memory controller clock is called the DDR clock. The CPU clock is called the SYS_CCB clock in the Freescale nomenclature, excuse me, the NXP nomenclature and those frequencies - they're single-ended clocks and they range, like the DDR from 66.66 MHz up to 100 MHz, and the CPU clocks range from 66.66 up to 133.33 MHz, in some cases. Those are single-ended LVCMOS input clocks. Additionally, some of the CPUs have a USB interface which may require a 24 MHz single-ended clock. And there's also an Ethernet interface built in, a one-gigabit Ethernet interface, that is, takes a 125 MHz single-ended clock as well and that's at 2.5 volts.

So, in the Layerscape series of CPUs which are based on the ARM core, Freescale has put into them, what they call a reduced oscillator mode where all the clocks over here basically are reduced by a single differential 100 MHz non-spreading clock, and this saves you from having to figure out and generate all these clocks. However, it has to be non-spread because the USB clock is also derived from it, so, if you're planning to use spread spectrum, you really can't use this mode. And, currently, it's only available in the Layerscape devices, not the legacy QorIQ devices.

So, that's the basics for the CPU and the memory controller. Then the SerDes is really dependent upon the particular CPU you're using and how many SerDes lanes you need in your design. So, the SerDes clocks, on the other hand, basically range from 125 MHz differential clock for Gigabit Ethernet, if you're using 10 Gigabit Ethernet, a 156.25 MHz clock is required. And then if you're using PCI Express, you'd use a standard 100 MHz PCI Express clock. All these happen to be differential and the number of SerDes lanes and their capabilities depends on the CPU you're using. So, this gives you an outline of how to just do a quick tally of what kind of clocks you need and in another video, I'll talk about the solutions that IDT has for NXP's devices.

Loading Loading

Product Selector Microcontrollers & Microprocessors

Applications

Design Resources

Support

Sample & Buy

About

Language

5P49V5923

VersaClock 5 Low Power Programmable Clock Generator

Features

Description

Parameters

Package Options

Filters

Filters

Software & Tools

Sample Code

Simulation Models