The IDT 8P34S1204i is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1204i is characterized to operate from a 1.8V power supply. Guaranteed low output-to-output and part-to-part skew characteristics make the 8P34S1204i ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of AC-coupled signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Four low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 1.2GHz
  • LVCMOS/LVTTL interface levels for the control input (input select)
  • Output skew: 14ps (typical)
  • Propagation delay: 265ps (typical)
  • Low additive phase jitter, RMS
  • fREF = 156.25MHz, 10kHz - 20MHz: 42fs (typical)
  • Device current consumption (IDD): 70mA (typical) @1.89V
  • Full 1.8V supply voltage
  • Lead-free (RoHS 6), 16-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

descriptionDocumentation

Title language Type Format File Size Date
star 8P34S1204 Datasheet Datasheet PDF 1.20 MB
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN# : PCN200016 Change Shipping Media on Select Package Product Change Notice PDF 2.97 MB
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel Product Change Notice PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
RF Timing Family Product Overview Overview PDF 331 KB
Clock Distribution Overview Overview PDF 217 KB
IDT Clock Generation Overview Overview PDF 1.83 MB