Overview

3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer.  With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions. 

• Phase-Lock Loop Clock Distribution for Synchronous DRAM applications
• Distributes one clock input to one bank of ten outputs
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    CSP2510CPG
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 C No Tube
    CSP2510CPG8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 C No Reel
    CSP2510CPGG
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 C Yes Tube
    CSP2510CPGG8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 C Yes Reel
    CSP2510CPGI
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 I No Tube
    CSP2510CPGI8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 24 I No Reel
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