Features
- Access time: 120ns
- Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control circuits
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
- Low power CMOS
- Active: 50mA
- Standby: 500µA
- Software data protection
- Protects data against system level inadvertent writes
- High speed page write capability
- Highly reliable Direct Write™ cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
- DATA polling
- Toggle bit polling
- X28HT010 is fuly functional @ +175°C
X28C010 Functional Diagram
Description
Support is limited to customers who have already adopted these products.
The Intersil X28C010/X28HT010 is a 128k x 8 EEPROM, fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable non-volatile memories, the X28C010/X28HT010 is a 5V only device. The X28C010/X28HT010 features the JEDEC approved pin out for byte-wide memories, compatible with industry standard EEPROMs. The X28C010/X28HT010 supports a 256-byte page write operation, effectively providing a 19µs/byte write cycle and enabling the entire memory to be typically written in less than 2. 5 seconds. The X28C010/X28HT010 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C010/X28HT010 supports Software Data Protection option. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years.
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- Guide
- Application NoteAI-generated Summary: The software controls clock synchronous communication using the 3-wire serial I/O (CSI mode) of the RL78 microcontroller's serial array unit as a single master. It supports MSB-first transfer and CPU-driven data transfer but lacks chip-select control and DMA or interrupt-driven transfer. The software operates under specified conditions with RL78/G14 and Renesas R1EX25xxx SPI EEPROM, using CS+ development environments and standard compiler settings.Related Files:
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- Application NoteAI-generated Summary: This document details the implementation of clock synchronous single master control using the SCI interface on RX family microcontrollers. It supports SPI mode with software-based MSB-first data transfer and both big and little endian formats. The sample code handles single master transmit, receive, and transmit/receive operations using CPU transfers only, without support for DMAC, EXDMAC, DTC, or interrupt-driven transfers. Chip select control is not included and must be implemented separately if needed.Related Files:
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- Application NoteRelated Files:
- Application NoteAI-generated Summary: The document details verified operating conditions for RX62N microcontrollers interfacing with various serial EEPROM and flash memory devices, specifying clock frequencies, voltages, development environments, and compiler settings. It explains RSPI module operation modes, focusing on clock synchronous (three-wire) operation, and describes hardware connections including pin functions and the need for external pull-up resistors and circuit matching components for high-speed operation.Related Files:
Recommended Documents (1)
Datasheets (1)
- Guide
Manuals & Guides (1)
- Application NoteAI-generated Summary: The software controls clock synchronous communication using the 3-wire serial I/O (CSI mode) of the RL78 microcontroller's serial array unit as a single master. It supports MSB-first transfer and CPU-driven data transfer but lacks chip-select control and DMA or interrupt-driven transfer. The software operates under specified conditions with RL78/G14 and Renesas R1EX25xxx SPI EEPROM, using CS+ development environments and standard compiler settings.Related Files:
- Application NoteRX Family SCIFA Clock Synchronous Single Master Control Module Using Firmware Integration TechnologyAI-generated Summary: The SCIFA FIT module enables easy integration of clock synchronous single master control into RX Family microcontrollers through APIs. It supports initialization, control, transmit/receive, interrupt handling, and error logging functions. Operation is confirmed on RX64M and RX71M groups with specified memory sizes, compiler settings, and development environments. Memory requirements vary by compiler version and endian mode.Related Files:
- Application NoteAI-generated Summary: The document details a sample program for RX family microcontrollers using RSPI for clock synchronous single master control via a three-wire serial communication method. It supports single-channel operation with MSB-first data transfer in both big and little endian formats. The code excludes chip select control and DMA transfers and allows normal or high-speed receive modes. Supervisor mode operation is required for high-speed mode, while normal mode supports both user and supervisor modes. The RSPI module's features and peripheral usage are outlined, including port requirements for slave device selection.Related Files:
- Application NoteAI-generated Summary: The document details control software for Renesas R1EX24xxx series serial EEPROMs using Renesas MCUs. It explains communication protocols including write, acknowledge polling, and read operations via I2C single master control software. The software supports multiple channels and slave devices, handles address conversion based on EEPROM capacity, and includes recovery functions for bus errors. It also outlines peripheral functions and usage examples for serial EEPROM communication.Related Files:
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Application Notes & White Papers (14)
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Product Notices (PCN, EOL, etc) (5)
- Technical Update
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- Technical Update
Errata & Technical Updates (5)
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