Features
- 28-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSGateEN and RESET inputs
- Low voltage operation: VDD = 1.7V to 1.9V
Description
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| SSTUAF32865AHLF | Obsolete | N/A | Out of Stock | CABGA | 160# | C | Yes | Tray |
| SSTUAF32865AHLFT | Obsolete | N/A | Out of Stock | CABGA | 160# | C | Yes | Reel |
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- Product Change NoticePDF 31 KB 7WDXRDKU4E7E-5-60594 May 02, 2016
- End Of Life NoticePDF 542 KB 7WDXRDKU4E7E-5-58957 May 05, 2015
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Datasheets (1)
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- Product Change NoticePDF 31 KB 7WDXRDKU4E7E-5-60594 May 02, 2016
- End Of Life NoticePDF 542 KB 7WDXRDKU4E7E-5-58957 May 05, 2015
Product Notices (PCN, EOL, etc) (2)
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