Overview
Design & Development
Software & Tools
Software & Tools
| Software title
|
Software type
|
Company
|
|---|---|---|
| C/C++ Compiler Package for SuperH Family C/C++ Compiler package for SuperH RISC engine Family. Simulator debugger and High-performance Embedded Workshop included.
|
Compiler/Assembler | Renesas |
| MISRA C Rule Checker SQMlint MISRA C Rule Checker (option)
|
Compiler/Assembler | Renesas |
| E10A-USB HS0005KCU01H for H-UDI Interface E10A-USB emulator not supporting AUD trace function.
|
Emulator | Renesas |
| E10A-USB HS0005KCU02H for AUD Trace Function E10A-USB emulator supporting AUD trace function.
|
Emulator | Renesas |
| High-performance Embedded Workshop Renesas integrated development environment (IDE) (for SuperH, RX, R8C, M32R, M16C, H8SX, H8S, H8, and 740 families).
|
IDE and Coding Tool | Renesas |
| Simulator Debugger for SuperH Family Simulator debugger for the SuperH RISC engine family [Support IDE : High-performance Embedded Workshop] (Note: This product is included in Compiler Package and is not available separately.)
|
Simulator | Renesas |
|
6 items
|
||
Sample Code
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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Support
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FAQs
-
Is there any limitation in the value set to the SH7710 FRQCR?
There are the values that can be set to FRQCR depending on the clock operation mode of CPU. Please see the table "Possible Combination of Clock Mode and FRQCR Values" on the chapter of on-chip oscillation circuits of hardware manual. Please select the setting value for FRQCR from this ...
Mar 23, 2009 -
Is there any note when RTC is not used?
When RTC is not used, the standby mode (software standby mode) cannot be canceled by IRQ, IRL, PINT and each interrupt of on-chip peripheral functions. Cancel the standby mode (software standby mode) by NMI or reset when RTC is not used.
Mar 25, 2009 -
Is the address error handling CPU when E-DMAC address error occur?
When E-DMAC address error is occurred, address error exception handling is not generated. When ADE bit is set under the condition that ADEIP bit (Address error interrupt permission) of EtherC/E-DMAC status interrupt permission register (EESIPR) is set to "1", EINT0 interruption is generated.
Mar 26, 2009