Overview
Description
The SH7046 Series single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration. The SH7046 series CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In addition, the SH7046 series includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports.
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FAQs
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Is it OK that AVcc pins and AVss pins are in the release state?
No, it is not OK. Do not put AVcc pins and AVss pins in the release state even when converter is not used. When A/D converter is not used, set as follows; AVcc=Vcc, AVss=Vss, AVref=Vcc. If the product has AVref pins, set as follows; AVref ...
Mar 23, 2009 -
Which mode should be used to perform synchronous operation?
MTU incorporates five channel timers consisting of channel 0-4. When performing 12-phase PWM output, set channel 0, 1, and 2 to PWM mode 2 and channel 3 and 4 to PWM mode 1. The output pins at this time are as follows; channel 0 : PWM mode 2 : TIOC0A ...
Mar 24, 2009 -
Is there any way to realize software interruption?
Please examine the following method. 1. Use trap instruction By executing TRAPA instruction, the exception handling vector table of vector no. 32-63 can be used. 2. Use dummy interrupt from on-chip peripheral function For example, the following interruption can be possible. •Timer interrupt (Overflow interruption of MTU, Compare ...
Mar 25, 2009