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Features

  • CPU:Cortex-M3(125MHz)
  • Voltage: 3V for IO, 1.15V for CPU
  • Package: 196pin LFBGA (12 x 12mm, 0.8 pitch)
  • Memory: SRAM 6MB with ECC
  • Ethernet port: max 3
  • Independent GMAC: 1 port
  • Ethernet Switch
  • EtherCAT slave controller
  • SERCOSⅢ slave controller

Description

RZ/N1L equipped with "Renesas R-IN engine (“R-IN engine”)" which is an accelerator for industrial Ethernet communication can be used for the communication parts of industrial network device where real - time responsibility is required. With integrated EtherCAT and Sercos III slave dedicated H/W, it is possible to handle a wide range of protocols.

Part NumberStatusSamplesStockPackageBudgetary Price (USD)Carrier TypeFamily NameSeries NameGroup NameCPU ArchitectureMain CPUSub CPUFloating Point UnitBit LengthProgram Memory (KB)Data Flash (KB)RAM (KB)ECC SRAMLead Count (#)Pitch (mm)Pkg. Dimensions (mm)Number of Supply Voltage(s) (#)Supply Voltage (V)I/O PortsDMAC or DTCDMA (ch)Temperature Sensor (ch) (#)Power-On ResetWatchdog Timer (ch)External Memory Bus (bit)DRAM I/FNPU3D GPUAcceleratorMOQTemp. Range (°C)External Interrupt Pins (#)LVD or PVDOperating Freq (Max) (MHz)Sub-clock (32.768 kHz)On-chip OscillatorEthernet speedEthernet (ch)EtherCat (ch) (#)USB Ports (#)USB FS (host ch/device ch)USB HS (host ch/device ch)USB SS (host ch/device ch)PCI Express (generation and ch)SCI or UART (ch)SPI (ch)QSPI (ch)OSPI (ch)I2C (#)I3C (ch)CAN (ch)CAN-FD (ch)WirelessIrDALIN (#)SDHI (ch)High Resolution Output TimerPWM Output (pin#)32-Bit Timer (ch)16-Bit Timer (ch) (#)8-Bit Timer (ch)Standby operable timerAsynchronous General Purpose Timer / Interval Timer (ch)RTC16-Bit A/D Converter (ch)14-Bit A/D Converter (ch)12-Bit A/D Converter (ch)10-Bit A/D Converter (ch)24-Bit Sigma-Delta A/D Converter (ch)16-Bit D/A Converter (ch)12-Bit D/A Converter (ch)10-Bit D/A Converter (ch) (#)8-Bit D/A Converter (ch)Analog Comparator (ch)OPAMP (ch) (#)PGA (ch)Capacitive Touch Sensing Unit (ch)Graphics LCD ControllerMIPI Interfaces (DSI) (ch)MIPI Interfaces (CSI) (ch)Camera I/F (Parallel)Image Codec2D Drawing EngineSegment LCD ControllerSSI (ch)Security & EncryptionDebug InterfaceRemarksMoisture Sensitivity Level (MSL)Country of AssemblyCountry of Wafer Fabrication
R9A06G034VGBA#AC1Last Time BuyN/AIn StockLFBGA1ku | $11.63Bulk (Tray)RZRZ/NN1LArmCortex-M3NoNo32006144KBYes196#0.8mm12 x 12 x 1.73#3 - 3.695DMAC160No1NoNoNoNoR-IN Engine1Tj = -40 to +1108#No125MHzNoNo10M/100M/1G3ch1#2#( 2 / 1 )( 2 / 1 )( 0 / 0 )No86102#020NoNo02No16412#0No0No0080000000000No00NoNoNoNo0NoJTAG/SWDIndustrial Ethernet3JAPANJAPAN

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DRAM & Flash Memory Solutions

Provides a comprehensive external memory solution for Renesas RZ and R‑Car families, supporting systems that require scalable off‑chip memory. Supported memory types include Serial NAND (Quad/Octal SPI, 512Mb to 8Gb, 1.8V and 3.3V, 100K/60K cycle endurance), ONFI NAND (ONFI 1.0, 1Gb to 8Gb, 1.8V and 3.3V, 100K/60K cycle endurance), DRAM (DDR2/3/4 from 512Mb to 32Gb and LPDDR2/3/4/4x/5/5x from 1Gb to 16Gb), and HyperRAM™ (HyperBus, 64Mb to 512Mb, 1.8V and 1.2V).

Support Communities

  1. RZ/N1L TCP throughput test with GOAL project TCP server.

    Hi,   I am trying to use RZ/N1L and the goal project "tcp_server" to have an easy TCP throughput test. I have downloaded the FW into the board without any modification, however I can't find a good way to test it.   I have tested several tools like ...

    Sep 4, 2019
  2. Mailbox stress test, RZN1D

    Hello,  My application uses a mailbox linked to shared memory block. In some cases, I am sending a mailbox at a high frequency every 1 mSec from CM3 to CA7. However, the CA7 runs code that takes 10mSec per iteration and only after it completes can i retrieve the mailbox ...

    Jan 27, 2025
  3. Bare-metal image on A7 core

    Hi,   I try to load the sample from SolKit.V1.4.3\Software\BaremetalDrivers to QSPI FLASH. I built a RAW binary for A7 core and try to upload it to QSPI by U-boot, according the document. USB DFU A7 set env command: => setenv bootcmd "dcache off&& ...

    Jul 30, 2020
View All Results from Support Communities (4)

Knowledge Base

  1. RZ Family: Can HW-RTOS-GMAC be used even if HW-RTOS does not used?

    ... is disabled manual configuration of HW-RTOS GMAC is required. Please refer the following section in the "RZ/N1D Group, RZ/N1S Group, RZ/N1L Group User’s Manual: R-IN Engine and Ethernet Peripherals": Section 3.5.1 Initialization  (1) Initial Settings of HW-RTOS GMAC ...

    Nov 14, 2025
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