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Overview

Description

The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial gateway control.

There are two package options. Please refer to the RZ/Five Overview for the differences in the functions supported by each.
13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
11 x 11 mm Package Part Number: R9A07G043F00GBG#BC0

The RZ/Five 13 x 13 mm package is also pin compatible with the RZ/G2UL (Type 1).

Features

  • 64-bit RISC-V/AX45MP (Single)
  • DDR4 or DDR3L memory interface
  • Memory error detection / correction (ECC)
  • Gigabit Ethernet 2ch
  • CAN interface (CAN-FD) 2ch
  • USB 2.0 interface 2ch
  • SD interface 2ch
  • AD converter 2ch
  • 13 x 13mm BGA package、11x11mm BGA package

Comparison

Applications

Documentation

Design & Development

Software & Tools

Software Downloads

Type Title Date
PCB Design Files Log in to Download ZIP 39.07 MB
PCB Design Files Log in to Download ZIP 11.25 MB
2 items

Boards & Kits

Models

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Diagram of ECAD Models

Models

Type Title Date
Model - IBIS Log in to Download ZIP 9.95 MB
Model - BSDL Log in to Download ZIP 12 KB
2 items

Product Options

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Support

Support Communities

Support Communities

Get quick technical support online from Renesas Engineering Community technical staff.
Browse FAQs

FAQs

Browse our knowledge base of common questions and answers.
Submit a Ticket

Submit a Ticket

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Support Communities

  1. Using RZ/Five-EVKIT as bare-metal

    Hello, I would like to give a try to the RZ/Five evaluation kit and I would like to know if it is possible to run a bare-metal application (e.g. by generating an executable and calling it from U-Boot). Thanks, Ricardo

    Jul 16, 2024
  2. RZ/Five eMMC boot support

    Dear Renesas Team, We are using Renesas RZ/Five Smarc-evaluation board, we are booting from SD-Card, but our requirement is to boot from eMMC. Please share us the procedure to boot from eMMC in RZ/Five Smarc-Evaluation board. also, Also during testing, we found that ...

    Apr 12, 2023
  3. Issue in PWM enabling in RZ/Five

    Hello, We are using VLP3.0.4 in RZ/Five processor. Trying to test PWM (MTU3) in RZ/Five using below commands. But PWM is not getting enabled.  cd /sys/class/pwm/pwmchip0/echo 0 > exportecho 1000000 > pwm0/periodecho 500000 > pwm0/ ...

    Sep 22, 2023
View All Results from Support Communities (21)

FAQs

  1. RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/Five: Small area implementation solution

    Our partner provides ultra-small modules that comply with the standard called OSM (Open Standard Module). In the 30x30 mmSq module, RZ/G MPU, PMIC, DDR-Memory, Flash-Memory and other components are mounted. Solutions provided by our partners are listed at RZ Partner Ecosystem Solutions.  https:// ...

    Jul 28, 2023
  2. RZ/Five: What methods do the Gigabit Ethernet interface of the RZ/Five support?

    Last Updated: 09/21/2022 Question: What methods do the Gigabit Ethernet interface of the RZ/Five support? Answer: MII and RGMII are supported. Suitable Products RZ/Five   Go to Japanese Go to Chinese

    Sep 21, 2022
  3. RZ/Five: Maximum transfer rate of SPI (Renesas Serial Peripheral Interface)

    Last Updated: 07/28/2023 Question: How much is the maximum transfer rate of RSPI (Renesas Serial Peripheral Interface)? Answer: The maximum transfer rate of RSPI is not decided only by the specifications of RZ/Five, but also depends on the specifications of the connected counter device ...

    Jul 28, 2023
View All Results from FAQs (11)

Videos & Training

RZ/Five provides a new platform for high-performance IoT Edge solutions. Learn the advantages of RISC-V CPU, and how to easily scale development across RISC-V and Arm cores.