RG5R188

The RG5R188 (MRCD) is a Gen 1 MRDIMM Registering Clock Driver for MRDIMM. Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a Buffer Command bus (BCOM) which control the data buffers. Each DDR5 MRDIMM 8800 MT/s would require 1 MRCD chip.

The Buffer Command bus is designed to enhance the performance of DDR5 MRDIMMs by managing the data flow between the host and the memory modules. This bus helps in optimizing signal integrity and achieving higher bandwidth per watt, which is particularly beneficial for applications such as AI training and inference workloads, high-performance computing (HPC), in-memory databases, and large language models (LLMs).

The Multiplexing Registering Clock Driver (MRCD) enhances the standard registering clock driver by processing an interleaved stream of DRAM commands at twice the typical RDIMM rate. It deinterleaves this command data stream and accurately directs it to the appropriate rank-specific outputs.

The Renesas MRCD (RG5R188) is compatible with DDR5 MRDIMM 8800 MT/s and it supports Intel Xeon 6 CPU’s available since 2024 and is qualified with multiple memory vendors. DDR5 MRDIMMs 8800 MT/s with Renesas MRCD (RG5R188) provides 39% more bandwidth and the MDB plays a key role in increasing Performance per watt for AI training and inference workloads.