Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NBG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.8 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| RoHS (RC32504A000GNK#BB0) | EnglishJapanese |
Product Attributes
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | SINGAPORE |
| 105°C Max. Case Temp. | 0 |
| Advanced Features | SyncE, DCO, Phase Adjust, External Feedback, Hitless Switching |
| App Jitter Compliance | 112G SerDes Jitter, PCIe Gen 6 |
| Application | Switch, Router, Medical Equipment, Broadcasting Video |
| Channels (#) | 1 |
| Clock Support | T-TSC, G.8262, G.8262.1 |
| Core Voltage (V) | 1.8V, 3.3V |
| Diff. Inputs | 1 |
| Diff. Outputs | 4 |
| Family Name | FemtoClock Clock Generator |
| Feedback Divider | 1 - 255 |
| Feedback Input | No |
| Fractional Output Dividers (#) | 1 |
| Input Freq (MHz) | 1 - 800 |
| Input Type | Crystal, LVPECL, HCSL, LVDS, CML, LVCMOS |
| Inputs (#) | 3 |
| Lead Compliant | No |
| Length (mm) | 4 |
| Longevity | 2040 Apr |
| Loop Bandwidth Range (Hz) | 0.1 - 12000 |
| MOQ | 490 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 10 - 1000 |
| Output Signaling | LVPECL, LVDS |
| Output Skew (ps) | 40 |
| Output Type | HCSL, LVDS, LVCMOS |
| Output Voltage (V) | 1.8 |
| Outputs (#) | 4 |
| Package Area (mm²) | 81 |
| Phase Jitter Max RMS (ps) | 0.1 |
| Phase Jitter Typ RMS (fs) | 79 |
| Phase Jitter Typ RMS (ps) | 0.079 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.8 |
| Pkg. Type | VFQFPN |
| Price (USD) | $9.59788 |
| Product Category | FemtoClock 2, Ultra-Low Jitter Clocks (<300 fs RMS), Extreme Performance Clocks (<150 fs RMS), Jitter Attenuators, Network Synchronization, PDH and SONET/SDH Clocks, Programmable Clocks |
| Prog. Clock | Yes |
| Prog. Interface | OTP, I2C, SPI |
| Published | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Selection Criteria | <150 fs RM |
| Spread Spectrum | No |
| Tape & Reel | No |
| Thickness (mm) | 0.8 |
| Width (mm) | 4 |
| Xtal Freq (KHz) | 25 - 80 |
| Xtal Inputs (#) | 1 |
Resources for RC32504A
Description
The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC, or FPGA that requires several reference clocks with a jitter performance of less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.