Overview
Description
The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC, or FPGA that requires several reference clocks with a jitter performance of less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.
Features
- Jitter below 100fs RMS (10kHz to 20MHz)
- Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
- PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
- Operates from a 25MHz to 80MHz crystal or XO
- APLL frequency independent of input/crystal frequency
- Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO)
- DPLL loop filter programmable from 0.1Hz to 12kHz
- DCO has a tuning granularity of < 1ppb
- Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
- Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
- Reference monitor qualifies/disqualifies input clock
- Programmable status output
- 4 differential/8 LVCMOS outputs
- Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
- Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
- Differential output swing is selectable: 400mV to 800mV
- Output clock phase individually adjustable in 100ps steps
- Output Enable input with programmable effect
- Supports up to 1MHz I²C or up to 20MHz SPI serial processor port
- Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
- 4mm × 4mm 24-VFQFPN package
Comparison
Applications
Design & Development
Software & Tools
Boards & Kits
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Support Communities
-
RC32504A
How to program the user configuration file in OTP of RC32504A? What hard ware connection I have to make and which software I should you?
Jan 9, 2025 -
Timing commander RC32504A
Hi! Do you have a timing commander personality file for the RC32504A ?
Jul 2, 2024 -
RC32504 APLL railing high/low after reference loss/restoration
I'm working on an SDR; I'm using three separate RC32504's to de-jitter clocks from an FPGA for use by an ADC, a DAC, and as a local oscillator reference. Both the reference clocks into the RC32504s are coming from the FPGA (overdriving the crystal input at ...
Dec 21, 2023
Videos & Training
Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.