Features
- PCIe Gen5 additive phase jitter: 5.9fs RMS
- PCIe Gen6 additive phase jitter: 3.5fs RMS
- PCIe Gen7 additive phase jitter: 2.4fs RMS
- DB2000Q additive phase jitter: 10fs RMS
- 12kHz to 20MHz additive phase jitter: 33fs RMS at 156.25MHz
- Power Down Tolerant (PDT) inputs
- Flexible Startup Sequencing (FSS)
- Automatic Clock Parking (ACP) upon loss of CLKIN
- Spread-spectrum tolerant
- CLKIN accepts HCSL or LVDS signal levels
- -40 °C to +105 °C, 1.8V ± 5% operation
- Pin or SMBus selectable:
- 33Ω, 85Ω, or 100Ω differential output impedance
- Output slew rate
- Output amplitude (A001 suffix)
- 9 SMBus addresses plus write protection
RC191xx Block Diagram
Description
The RC19102 is a 1.8V 2-output PCIe Gen7 buffer that is backward compatible with earlier PCIe generations. The RC19102 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 400 |
| Diff. Inputs | 1 |
| Power Consumption Typ (mW) | 50 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Output Type | LP-HCSL |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 1 - 400 |
| Additive Phase Jitter Typ RMS (fs) | 33 |
| Function | Multiplexer |
| Input Type | LVDS, HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8V, 1.8V |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 20 | 0.4 |
Product Comparison
| RC19102A | 9DBL0252 | RC19002 | |
| Core Voltage (V) | 1.8 | 3.3 | 3.3 |
| Output Impedance | 33, 85, 100 | 85 | 85, 100 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7 |
| VOUT Slew-rate Control | Yes | No | Yes |
| Additive Jitter | 3.5fs | 13fs | 3.4fs |
| VOUT Amplitude Control | Yes | No | No |
Applications
- Cloud/High-performance computing
- nVME storage
- Networking
- Accelerators
| Part Number | Status | Samples | Longevity | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RC19102AGNT#BD0 | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 1ku | $1.25 | 20# | Tray | 1 | 0 | 624# | Yes | e3 Sn | -40 to 105°C | TAIWAN | SINGAPORE |
| RC19102AGNT#KD0 | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 1ku | $1.25 | 20# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 105°C | TAIWAN | SINGAPORE |
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- Application NotePDF 2.66 MB R31AN0080EU0102 Rev.1.02 Jun 02, 2026AI-generated Summary: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- Application NotePDF 2.66 MB R31AN0080EU0102 Rev.1.02 Jun 02, 2026AI-generated Summary: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.View More (10)
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The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
The 9ZXL1951D is designed to create clocks for PCI Express Generation 4. This video demonstrates how the reference clock for the 9ZXL1951D does not need to be PCI Express Gen4 compliant. When using the Low Bandwidth mode, the 9ZXL1951D will attenuate jitter so its output clocks still pass PCI Express Gen4, even when the input clock only passes PCI Express Gen3. This is most useful when the clock has spread spectrum modulation because it is very difficult to make a very low noise spreading clock.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
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