Features
- Distribution, fanout, phase-delay of clock, and SYSREF signals
- Low output noise floor: -163dBc/Hz (245.76MHz)
- Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz
- Phase alignment mode across multiple buffers with any frequency divider setting
- Configuration through 3-wire SPI interface
- Supply voltage:
- 3.3V core and signal I/O
- 1.8V digital control SPI I/O (3.3V-tolerant inputs)
- Reference inputs are fail-safe
- Provides four output channels with a total of 16 differential outputs
- Outputs channels include:
- Dedicated clock outputs
- Outputs configurable as SYSREF outputs with individual phase delay stages, or configurable as additional clock outputs
- Clock outputs are powered-on/enabled at startup
- QREF_r (SYSREF) outputs disabled at startup
- Each clock channel contains:
- Frequency Dividers: ÷1, ÷2, ÷3, ÷4, ÷6, ÷8, ÷12,÷16, ÷24
- Clock phase delay circuits, delay unit is the clock period; 256 steps
- SYSREF: Configurable precision phase delay circuits: 8 steps of 131ps, 262ps, 393ps, or 524ps
- Flexible differential outputs:
- LVDS/LVPECL/AC-HCSL
- Amplitude configurable for LVDS and LVPECL
- Power-down modes for unused outputs
- Supports DC and AC coupling
- QREF_r (SYSREF) output pre-bias feature to prevent glitches when turning output on or off
- Package: 64-VFQFPN (9.0 × 9.0 × 0.85 mm)
- Ambient temperature range: -40°C to +105°C (case)
Description
The RC18016A is a fully integrated, clock and SYSREF signal sixteen output fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliances. The main function of the device is the distribution and fanout of high-frequency clocks and low-frequency system reference signals generated by a JESB204B/C clock generator such as the RC38312A, extending its fanout capabilities and providing additional phase-delay. The RC18016A is optimized to deliver very low phase noise clocks and precise, phase-adjustable SYSREF synchronization signals. Low-skew outputs, low device-to-device skew characteristics and fast output rise/fall times help the system design to achieve deterministic clock and SYSREF phase relationship across devices.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 105°C (Tc ≤ 105°C) |
| Product Category | Clock Buffers & Drivers, RF Buffers |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 9.0 x 9.0 x 0.9 | 64 | 0.5 |
Applications
- Wireless infrastructure applications: 4G, 5G, and mmWave
- Frequency divider synchronization across multiple devices
- Ideal clock driver for jitter-sensitive ADC and DAC circuits
- Radar, imaging, instrumentation, and medical
| Part Number | Status | Samples | Longevity | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RC18016AGN1#BB0 | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 64# | Tray | 3 | 0 | 207# | Yes | e3 Sn | -40 to 105°C (Tc ≤ 105°C) |
| RC18016AGN1#KB0 | Active | N/A | 2040 Apr | Out of Stock | VFQFPN | 64# | Reel | 3 | 3000# | 0 | Yes | e3 Sn | -40 to 105°C (Tc ≤ 105°C) |
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- Manual - HardwarePDF 2.51 MB R31UH0031EU0100 Rev.1.00 Jul 05, 2024
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