RBN200N180S2HFWA

AI-generated Summary: Wire bonding damage occurs during the assembly of bare die or wafer IGBTs when improper bonding conditions cause defects such as misaligned bonds, chip surface scratches, or cracks. Excessive bonding stress can damage cells visibly or internally, affecting device performance and reliability. Evaluating bonding limits by adjusting power and force ensures optimal bonding strength without damage. Careful verification of bonding conditions improves yield and prevents failures like turn-off malfunctions caused by localized damage.

AI-generated Summary: The document details procedures for assembling IGBT modules, emphasizing proper installation order to prevent damage and ensure reliability. It covers mounting methods for pin-fin copper base and flat copper base modules, focusing on cooling water channel design, O-ring sealing for watertightness, and corrosion prevention. It highlights the importance of minimizing gaps in cooling channels to maximize flow velocity and prevent leakage. The document also discusses thermal grease application for flat copper base modules and recommends testing for leakage resistance and galvanic corrosion to ensure long-term durability.

AI-generated Summary: The document details specifications and usage guidelines for a 6-in-1 IGBT module designed for 3-phase inverters in xEV applications. It covers the module's structure, including IGBTs, FRDs, and thermistors, and explains cooling methods using flat or pin-finned copper bases with water or grease cooling. The document highlights thermal fatigue concerns due to material expansion differences and provides detailed datasheet parameters for IGBTs and FRDs, including absolute maximum ratings and electrical characteristics essential for safe and reliable operation.

AI-generated Summary: Wafer testing for IGBT chips bridges the gap between wafer-level and module-level testing by applying higher test currents closer to module conditions, improving overall module quality. Key failure modes include gate failure, detected through high-voltage DC screening to identify oxide defects, and SOA failure, identified via AC switching tests to detect transient current concentration and latch-up failures. Gate screening applies stress beyond normal operation to reduce early failures and ensure long-term reliability. L-load AC screening rejects chips prone to latch-up by simulating switching conditions, enhancing yield and reducing costs in module manufacturing.