Description
The R8C/18 Group is supported only for customers who have already adopted these products. The RL78/G12 Group is recommended for new designs.
This MCU is built using the high-performance silicon gate CMOS process using the R8C/Tiny Series CPU core and is packaged in a 20-pin plastic molded LSSOP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1Mb of address space, it is capable of executing instructions at high speed. Furthermore, the data flash ROM (1KB × 2 blocks) is embedded in the R8C/17 group. The difference between the R8C/16 and R8C/17 groups is only the existence of the data flash ROM. Their peripheral functions are the same.
Applications
- Electric Household Appliance
- Office Equipment
- Housing Equipment (Sensor / Security)
- General Industrial Equipment
- Audio
| Part Number | Status | Samples | Stock | RoHS | Package | RAM (KB) | Lead Count (#) | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|
| R5F21181DD#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SDIP | 0.375KB | 20# | -20 to +85 |
| R5F21181DSP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 0.375KB | 20# | -40 to +85 |
| R5F21181DSP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.375KB | 20# | -40 to +85 |
| R5F21181SP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 0.375KB | 20# | -20 to +85 |
| R5F21181SP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.375KB | 20# | -20 to +85 |
| R5F21182DD#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SDIP | 0.5KB | 20# | -20 to +85 |
| R5F21182DSP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 0.5KB | 20# | -40 to +85 |
| R5F21182DSP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.5KB | 20# | -40 to +85 |
| R5F21182NP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | HWQFN | 0.5KB | 28# | -20 to +85 |
| R5F21182NP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | HWQFN | 0.5KB | 28# | -20 to +85 |
| R5F21182SP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 0.5KB | 20# | -20 to +85 |
| R5F21182SP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.5KB | 20# | -20 to +85 |
| R5F21183DD#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SDIP | 0.75KB | 20# | -20 to +85 |
| R5F21183DSP#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.75KB | 20# | -40 to +85 |
| R5F21183DSP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.75KB | 20# | -40 to +85 |
| R5F21183NP#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | HWQFN | 0.75KB | 28# | -20 to +85 |
| R5F21183NP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | HWQFN | 0.75KB | 28# | -20 to +85 |
| R5F21183SP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 0.75KB | 20# | -20 to +85 |
| R5F21183SP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 0.75KB | 20# | -20 to +85 |
| R5F21184DD#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | SDIP | 1KB | 20# | -20 to +85 |
| R5F21184DSP#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 1KB | 20# | -40 to +85 |
| R5F21184DSP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 1KB | 20# | -40 to +85 |
| R5F21184NP#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | HWQFN | 1KB | 28# | -20 to +85 |
| R5F21184NP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | HWQFN | 1KB | 28# | -20 to +85 |
| R5F21184SP#U0 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 1KB | 20# | -20 to +85 |
| R5F21184SP#W4 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 1KB | 20# | -20 to +85 |
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- Application NoteAI-generated Summary: The document explains how to register and uninstall Call Walker within the High-performance Embedded Workshop (HEW). It guides users to launch HEW without opening a workspace, access the Tools Administration menu, and register the Call Walker tool by specifying the registration file path. After registration, Call Walker version 2.3 appears in the menu. Upon uninstalling HEW, users must manually delete the remaining Call Walker directory. It also provides Renesas Electronics website and contact information for support. The revision history notes the first edition release date.
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- Application NoteAI-generated Summary: The document specifies the serial communication protocols for the R8C/1x and 2x Series microcontrollers in standard serial I/O modes 2 and 3. It details boot program operations including initial settings, communication with a serial programmer, and control commands for flash memory. Communication formats are asynchronous, with defined data transfer structures. Pin assignments and connection examples for both modes are provided. Initial settings cover selecting communication mode based on the MODE pin level after reset and adjusting the bit rate to 9600 bps through a defined handshake process with the serial programmer.
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- DatasheetR8C/18, R8C/19 Group DatasheetRECOMMENDED
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- Application NoteAI-generated Summary: The document explains how to register and uninstall Call Walker within the High-performance Embedded Workshop (HEW). It guides users to launch HEW without opening a workspace, access the Tools Administration menu, and register the Call Walker tool by specifying the registration file path. After registration, Call Walker version 2.3 appears in the menu. Upon uninstalling HEW, users must manually delete the remaining Call Walker directory. It also provides Renesas Electronics website and contact information for support. The revision history notes the first edition release date.
- Application NoteAI-generated Summary: The document specifies the serial communication protocols for the R8C/1x and 2x Series microcontrollers in standard serial I/O modes 2 and 3. It details boot program operations including initial settings, communication with a serial programmer, and control commands for flash memory. Communication formats are asynchronous, with defined data transfer structures. Pin assignments and connection examples for both modes are provided. Initial settings cover selecting communication mode based on the MODE pin level after reset and adjusting the bit rate to 9600 bps through a defined handshake process with the serial programmer.
- Application NotePDF 126 KB R20AN0090ES0100 Rev.1.00 Mar 01, 2010AI-generated Summary: The system timer in MR8C/4 tracks elapsed time in an RTOS by generating periodic interrupts, incrementing a tick counter. The timer's resolution depends on application needs, hardware limitations, and counter storage. MR8C/4 uses a 6-byte counter allowing up to 8925 years of tick counting at 1ms resolution. Hardware timer inaccuracies require adjustments to ensure minimum delay durations. Users configure the system timer by selecting hardware timers, setting interrupt priorities, and defining interrupt vectors. The system timer manages time-based functions and is optional if no time management is used.
- Application NotePDF 938 KB R20AN0089ES0100 Rev.1.00 Mar 01, 2010AI-generated Summary: MR8C/4 provides two types of time event handlers: cyclic handlers for repetitive events at fixed intervals, and alarm handlers for one-shot events at specified times. These handlers operate independently from tasks, executing in non-task contexts with priority between interrupts and dispatchers. Time event handlers must be statically created in configuration files and require the CPU to be unlocked for activation. Accuracy depends on system timer resolution, with R8C devices supporting up to 1 ms resolution. Cyclic handlers can be used to trigger tasks periodically without reprogramming timers.
- Application NotePDF 695 KB R20AN0088ES0100 Rev.1.00 Mar 01, 2010AI-generated Summary: Interrupts enable embedded systems to handle time-critical tasks by signaling the processor to pause current operations and address urgent events. There are hardware and software interrupts, with hardware interrupts further divided into special and peripheral I/O types. The R8C family uses two interrupt vector tables: fixed and relocatable, which store interrupt service routines and their properties. Interrupt priority levels allow nested interrupts, and interrupts can be maskable or non-maskable, with NMIs reserved for critical system events.View More (87)
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- IDE and Coding ToolRenesas integrated development environment (IDE) (for SuperH, RX, R8C, M32R, M16C, H8SX, H8S, H8, and 740 families).
- Compiler/AssemblerC/C++ Compiler Package for R8C Family and M16C Family (R32C/M32C/M16C) , * Packed the following three compiler packages : [Content] C Compiler Package for R32C Series, C Compiler Package for M32C Series [M3T-NC308WA], and C/C++ Compiler Package for M16C Series and R8C Family [M3T-NC30WA]. They are bundled with the simulator debugger and High-performance Embedded Workshop.
- EmulatorOn-Chip Debugging Emulator for M16C and H8 families. Available as a flash memory programmer for M16C and 740(QzROM) families also by using with Flash Development Toolkit. Note that the H8 family MCUs support the debugging features and that the 740 family MCUs support only the programming features. * Successor : E8a
- EmulatorOn-Chip Debugging Emulator for R8C, M16C, H8S, H8 and 740 families. E8a is also used as a device programmer for Renesas microcomputers. This product is E8 emulator's successor.
- EmulatorEmulator for M16C Family [Overseas Standards Compliant]. Support for all operating frequencies of M16C.
- Programmer (Unit/SW)On-chip debugging emulator available as a flash memory programmer [Available flash programming software: Flash Development Toolkit]
- Programmer (Unit/SW)On-chip debugging emulator available as a flash memory programmer [Available flash programming software: Flash Development Toolkit] [Support MCU/MPU and devices: SuperH RISC engine, R8C, M16C, H8SX, H8S, H8, 740]
- Programmer (Unit/SW)Flash memory programming software. [Support MCU/MPU and devices: SuperH RISC engine, RX, R8C, M16C, H8SX, H8S, H8, 740]
- Programmer (Unit/SW)Connected with a Flash Programmer, these IC Socket Boards enable reprogramming of the on-chip Memory before mounting.
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- SimulatorSimulator Debugger for M16C/60, M16C/30, M16C/Tiny, M16C/20, M16C/10 Series and R8C Family [Support IDE : High-performance Embedded Workshop] (Note: This product is included in Compiler Package and is not available separately.)
- ITRON OSμITRON4.0 Specification real-time OS for M32C/80, M16C/80 Series [Required IDE :High-performance Embedded Workshop]
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- IDE and Coding ToolRenesas integrated development environment (IDE) (for SuperH, RX, R8C, M32R, M16C, H8SX, H8S, H8, and 740 families).
- Compiler/AssemblerC/C++ Compiler Package for R8C Family and M16C Family (R32C/M32C/M16C) , * Packed the following three compiler packages : [Content] C Compiler Package for R32C Series, C Compiler Package for M32C Series [M3T-NC308WA], and C/C++ Compiler Package for M16C Series and R8C Family [M3T-NC30WA]. They are bundled with the simulator debugger and High-performance Embedded Workshop.
- EmulatorOn-Chip Debugging Emulator for M16C and H8 families. Available as a flash memory programmer for M16C and 740(QzROM) families also by using with Flash Development Toolkit. Note that the H8 family MCUs support the debugging features and that the 740 family MCUs support only the programming features. * Successor : E8a
- EmulatorOn-Chip Debugging Emulator for R8C, M16C, H8S, H8 and 740 families. E8a is also used as a device programmer for Renesas microcomputers. This product is E8 emulator's successor.View More (18)
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Knowledge Base
-
(R8C) Are there any hardware precautions for accurate A/D conversion?
In order to perform A/D conversion, it is necessary to fully charge the internal capacitor, but if the impedance of the A/D conversion target is high, the discharge and charge will take time and the conversion value will not be accurate. For correct A/D ...
Jun 19, 2006 -
Can a parallel programmer verify the program in condition the ROM code protect is enabled?
The ROM code protect is enabled at the first MCU reset after setting the ROM code protect function. If there is no reset after writing the program, the program can be verified. Contact the parallel programmer manufacturer for programmer specifications.
Dec 26, 2017 -
What is the reason of reset caused by the watchdog timer?
The RAM is also initialized in the start-up file (ncrt0.a30). It might need several tens of milliseconds to initialize the RAM because of the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. Therefore, please refresh the watchdog timer ...
Dec 26, 2017
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