Package Information
| Lead Count (#) | 48 |
| Pkg. Code | LEN |
| Pitch (mm) | 0.5 |
| Pkg. Type | QFN |
| Pkg. Dimensions (mm) | 7.01 x 7.01 x 0.90 |
Environmental & Export Classifications
| Pb (Lead) Free | No |
| ECCN (US) | 3A991.c.3 |
| HTS (US) | 8542.39.0030 |
| RoHS (ISLA214S50IR1Z) | Download |
| Moisture Sensitivity Level (MSL) |
Product Attributes
| Lead Count (#) | 48 |
| Carrier Type | Tray |
| Pb (Lead) Free | No |
| Temp. Range (°C) | -40 to +85°C |
| Channels (#) | 1 |
| Conversion Rate (Max) (kSPS) | 500000 |
| Differential NonLinearity LSB | 0.35 |
| Digital Supply Voltage (V) | 1.8 - 1.8 |
| Integral NonLinearity LSB | 2.4 |
| Interface | JESD204B High Speed Serial |
| Length (mm) | 7 |
| MOQ | 10 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 0.90 |
| Pkg. Type | QFN |
| Power Consumption (mW) | 1060 |
| Qualification Level | Standard |
| Resolution (bits) | 14 |
| SFDR (dB) (dB) | 87 |
| SNR (dbFS) | 73.1 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Thickness (mm) | 0.9 |
| Width (mm) | 7 |
Resources for ISLA214S50
Description
The ISLA214S50 is a series of low-power, high-performance, 14-bit, analog-to-digital converters. Designed with FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 500MSPS. The ISLA214S50 is part of a pin-compatible family of 12-, 14-, and 16-bit A/Ds with maximum sample rates ranging from 125MSPS to 500MSPS. The family minimizes power consumption while providing state-of-the-art dynamic performance. The device utilizes two time-interleaved 250MSPS unit ADCs to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Intersil Interleave Engine (I2E) performs automatic correction of offset, gain, and sample time mismatches between the unit ADCs to optimize performance. The ISLA214S50 offers a highly configurable, JESD204Bcompliant, high speed serial output link. The link offers data rates up to 4. 375 Gbps per lane and multiple packing modes. The link can be configured to use two or three lanes to transmit the conversion data, allowing for flexibility in the receiver design. The JESD204 transmitter also provides deterministic latency and multi-chip time alignment support to satisfy complex synchronization requirements. A serial peripheral interface (SPI) port allows for extensive configurability of the ADC and its JESD204B transmitter including access to its built-in link and transport-layer test patterns as well as the programmable clock divider, enabling 2x harmonic clocking. The ISLA214S50 is available in a space-saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C)