Package Information
| Pitch (mm) | 0.5 |
| Lead Count (#) | 8 |
| Pkg. Dimensions (mm) | 3.00 x 3.00 x 0.75 |
| Pkg. Code | LPF |
| Pkg. Type | TDFN |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542390001 |
| RoHS (ISL89163FRTAZ-T) | Download |
Product Attributes
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 3.0 x 3.0 x 0.75 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Temp. Range | -40 to +125°C |
| Country of Assembly | Malaysia |
| Country of Wafer Fabrication | Taiwan |
| Drivers (#) | 2 |
| Fall Time | 0.02 |
| IS (mA) | 5 |
| Input Signal (Max) | 16 |
| Input Signal (Min) | 0 |
| Input Signal Range | 0 to 16 |
| Input Supply (Max) (VP) | 16 - 16 |
| Input Supply Range (V) | 4.5 - 16 |
| Input Voltage (Max) (V) | 16 |
| Length (mm) | 3.0 |
| MOQ | 6000 |
| Operating Freq (Max) (MHz) | 10 |
| Output Signal (Max) (V) | 16 |
| Output Signal (Min) (V) | 0 |
| Output Signal Range | 0 to +16 |
| Parametric Category | Low-Side FET Drivers |
| Peak Output Current IPK (A) | 6 |
| Pkg. Type | TDFN |
| Qualification Level | Standard |
| RDS (ON) (Ohms) | 2 |
| Rise Time (μs) | 20 |
| Thickness (mm) | 0.75 |
| Turn Off Delay (ns) | 25 |
| Turn On Delay (ns) | 25 |
| VBIAS (Min) (V) | 4.5 |
| Width (mm) | 3.0 |
Description
The ISL89163, ISL89164, and ISL89165 are high-speed, 6A, dual channel MOSFET drivers with enable inputs. Precision thresholds on all logic inputs allow the use of external RC circuits to generate accurate and stable time delays on both the main channel inputs, INA and INB, and the enable inputs, ENA and ENB. The precision delays capable of these precise logic thresholds makes these parts very useful for dead-time control and synchronous rectifiers. Note that the enable and input logic inputs can be interchanged for alternate logic implementations. Three input logic thresholds are available: 3. 3V (CMOS), 5. 0V (CMOS or TTL compatible), and CMOS thresholds that are proportional to VDD. At high switching frequencies, these MOSFET drivers use very little internal bias currents. Separate, non-overlapping drive circuits are used to drive each CMOS output FET to prevent shoot-through currents in the output stage. The start-up sequence is designed to prevent unexpected glitches when VDD is being turned on or turned off. When VDD ~1V, an internal 10kΩ resistor between the output and ground helps to keep the output voltage low. When ~1V VDD UV, both outputs are driven low with very low resistance and the logic inputs are ignored. This insures that the driven FETs are off. When VDD > UVLO, and after a short delay, the outputs now respond to the logic inputs.