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Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

Package Information

CAD Model:View CAD Model
Pkg. Type:DIE
Pkg. Code:
Lead Count (#):
Pkg. Dimensions (mm):
Pitch (mm):

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)
Pb (Lead) FreeNo
ECCN (US)EAR99
HTS (US)8542.39.0090
RoHS (ISL70001SRHVX)EnglishJapanese

Product Attributes

Pkg. TypeDIE
Qualification LevelClass V
DLA SMD5962R0922501V9A
Pb (Lead) FreeNo
MOQ10
Temp. Range (°C)-55 to +125°C
CAGE code34371
Control ModePeak Current Mode
Control TypeCurrent Mode
DSEE (MeV·cm2/mg)86
Die Sale Availability?Yes
Duty Cycle (%)90 - 90
FlowRH Hermetic
IOUT Rail 1 (max) (A)6
IQ [Rail 1] (µA)2000
Input Voltage (Max) [Rail 1] (V)5.5 - 5.5
Input Voltage (Min) [Rail 1] (V)3
Lead CompliantNo
No-Load Operating Current40 mA
Output Current (Max) [Rail 1] (A)6
Output Voltage (Max) [Rail 1] (V)4.675
Output Voltage (Min) (V)0.6
Output Voltage (Min) [Rail 1] (V)0.6
Outputs (#)1
PORYes
PROTO Availability?Yes
Peak Efficiency (%)94
Quiescent Current2mA
RatingSpace
SYNCH CapabilityYes
Supply Voltage Rail 1 (max) (V)5.5
Supply Voltage Rail 1 (min) (V)3
Switching Frequency (MHz)1 - 1
Switching Frequency (max) (kHz)1000
Switching Frequency (min) (kHz)1000
TID HDR (krad(Si))100
Tape & ReelNo
Topology [Rail 1]Buck
VOUT Rail 1 (max) (V)4.675
VOUT Rail 1 (min) (V)0.6

Description

The ISL70001SRH is a radiation hardened and Single-Event Effect (SEE) hardened high-efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single-chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145°C. High integration and class-leading radiation tolerance make the ISL70001SRH an ideal choice to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large-scale digital ICs, like field-programmable gate arrays (FPGAs) that require separate core and I/O voltages. In applications where the ENABLE input is tied high to PVIN we recommend that the input voltage ramp rate be equal to or greater than 10V/ms. This is to prevent unwanted voltage from prematurely appearing on the output. For a PVIN voltage that has a slower ramp rate or is stepped up, we recommend the use of the ISL70001ASEH. Ensuring that the ENABLE input is held low until the chosen VINPOR is satisfied will prevent this ‘false start’.