Features
- Speed grades 130M and 210+MSPS
- Low power 103mW with 20mA output at 130MSPS
- Adjustable full-scale output current 2mA to 20mA
- +3.3V power supply
- 3V LVCMOS compatible inputs
- Excellent spurious free dynamic range (71dBc to Nyquist, fS = 130MSPS, fOUT = 10MHz)
- UMTS adjacent channel power = 65dB at 19.2MHz
- EDGE/GSM SFDR = 83dBc at 11MHz in 20MHz window
- Pin compatible, 3.3V, lower power replacement for the AD9750 and HI5760
- Pb-free available
Description
Support is limited to customers who have already adopted these products.
The ISL5761 is a 10-bit, 130/210+MSPS (Mega Samples Per Second), CMOS, high-speed, low power, D/A (digital-to-analog) converter, designed specifically for use in high-performance communication systems such as base transceiver stations utilizing 2.5G or 3G cellular protocols. This device complements the ISL5x61 family of high-speed converters, which include 10, 12 and 14-bit devices.
Applications
- Cellular infrastructure - Single or multi-carrier: IS-136, IS- 95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
- BWA infrastructure
- Medical/Test instrumentation
- Wireless communication systems
- High resolution imaging systems
- Arbitrary waveform generators
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Conversion Rate (Max) (kSPS) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ISL5761/2IAZ | Obsolete | N/A | In Stock | TSSOP | 28# | Tube | 3 | 210000kSPS | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | -40 to +85°C |
| ISL5761IAZ | Obsolete | N/A | Out of Stock | TSSOP | 28# | Tube | 3 | 130000kSPS | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | -40 to +85°C |
Filters
Applied Filters
- Product Change NoticePDF 98 KB PCN12094 Dec 19, 2012
- Application NotePDF 503 KB an9675 Aug 13, 1999AI-generated Summary: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- Application NotePDF 1.08 MB an002 Nov 19, 1998AI-generated Summary: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- Application NotePDF 287 KB an9705 Feb 21, 1997AI-generated Summary: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
Recommended Documents (1)
Datasheets (1)
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- Application NotePDF 503 KB an9675 Aug 13, 1999AI-generated Summary: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- Application NotePDF 1.08 MB an002 Nov 19, 1998AI-generated Summary: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- Application NotePDF 287 KB an9705 Feb 21, 1997AI-generated Summary: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
Application Notes & White Papers (3)
- Product Change NoticePDF 98 KB PCN12094 Dec 19, 2012
Product Notices (PCN, EOL, etc) (3)
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Marketing Collateral (1)
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Renesas Boards & Kits
14-Bit, +3.3V, 210/130MSPS High-Speed D/A Converter Evaluation Board
The ISL5761EVAL1 evaluation board provides a quick and easy method for evaluating the ISL5761 10-bit, 130/210MSPS high-speed digital-to-analog converters (DACs). The ISL5761EVAL1 is populated with an SOIC package and the board is configured so that the converter outputs differential current into... Read More
14-Bit, +3.3V, 210/130MSPS High-Speed D/A Converter Evaluation Board
The ISL5761EVAL2 evaluation board provides a quick and easy method for evaluating the ISL5761 130/210MSPS high-speed digital-to-analog converter (DAC). The ISL5761EVAL2 is populated with a TSSOP package. The board is configured so that the converter outputs differential current into a... Read More