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Features

  • Throughput Rate 125MSPS
  • Low Power 165mW at 5V, 27mW at 3V
  • Power Down Mode 23mW at 5V, 10mW at 3V
  • Integral Linearity Error ±0.25 LSB
  • Adjustable Full Scale Output Current 2mA to 20mA
  • SFDR to Nyquist at 10MHz Output 60dBc
  • Internal 1.2V Bandgap Voltage Reference
  • Single Power Supply from +5V to +3V
  • CMOS Compatible Inputs
  • Excellent Spurious Free Dynamic Range
  • Pb-free Available

Description

The HI5660 is an 8-bit, 125MSPS, High-Speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. For an equivalent performance dual version, see the HI5628. This device complements the HI5X60 family of High-Speed converters offered by Intersil, which includes 8, 10, 12, and 14-bit devices.

Applications

  • Medical Instrumentation
  • Wireless Communications
  • Direct Digital Frequency Synthesis
  • Signal Reconstruction
  • Test Instrumentation
  • High Resolution Imaging Systems
  • Arbitrary Waveform Generators
Part NumberStatusSamplesStockRoHSPackageLead Count (#)Carrier TypeMoisture Sensitivity Level (MSL)Conversion Rate (Max) (kSPS)Pitch (mm)Pkg. Dimensions (mm)Pb (Lead) FreePb Free CategoryTemp. Range (°C)
HI5660/6IAZObsoleteN/AIn StockContactTSSOP28#Tube360000kSPS0.7mm9.7 x 4.4 x 0.00YesPb-Free 100% Matte Tin Plate w/Anneal-e3-40 to +85°C
HI5660/6IAZ-TObsoleteN/AIn StockContactTSSOP28#Reel360000kSPS0.7mm9.7 x 4.4 x 0.00YesPb-Free 100% Matte Tin Plate w/Anneal-e3-40 to +85°C
HI5660IBZObsoleteN/AIn StockRoHS:EN
SOICW28#Tube3125000kSPS1.3mm17.9 x 7.5 x 0.20YesPb-Free 100% Matte Tin Plate w/Anneal-e3-40 to +85°C

Support Communities

  1. HI5660 DAC proagation delay

    Hi all, we facing a issue with propagtion delay of the HI5660 digital analog converter. Regarding to timing diagram (fig.1) in datasheet, the data will be latched with rising edge of clock and the output willl be change within the specified timming (small propagation delay). But from practicle test ...

    May 6, 2020
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