Name: 9ZXL0651E - 6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer
Brand: Renesas Electronics Corporation
SKU: 9ZXL0651E - 6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer
Price: 2.65877 USD
Availability: InStock

Features

LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm² of area
PCIe Gen 1–5 compliance
6 OE# pins; hardware control of each output
Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for EMI reduction
100MHz PLL Mode; UPI support
5mm × 5mm 40-VFQFPN package; small board footprint

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Description

The 9ZXL0651E is a second-generation, enhanced-performance DB800ZL derivative. The part is a pin-compatible upgrade to the 9ZXL0651A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

Parameters

Attributes	Value
Temp. Range (°C)	-40 to 85°C

Package Options

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
VFQFPN	5.0 x 5.0 x 0.9	40	0.4

Applications

Servers/High-performance Computing
nVME Storage
Networking
Accelerators
Industrial Control

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.

Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.

The 9ZXL1951D is designed to create clocks for PCI Express Generation 4. This video demonstrates how the reference clock for the 9ZXL1951D does not need to be PCI Express Gen4 compliant. When using the Low Bandwidth mode, the 9ZXL1951D will attenuate jitter so its output clocks still pass PCI Express Gen4, even when the input clock only passes PCI Express Gen3. This is most useful when the clock has spread spectrum modulation because it is very difficult to make a very low noise spreading clock.

Related Resources

A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.

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9ZXL0651E

6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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