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9QXL2001C

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Product Longevity: 2040

20-Output Enhanced DB2000QL PCIe Clock Buffer

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Features

  • 8 OE# pins provide hardware control of 8 outputs
  • 20 SMBus bits allow software control of each output
  • 3-wire side-band interface provides serial control of all 20 outputs at a 25MHz rate
  • Outputs remain Low/Low when powered up with a floating input clock
  • Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
  • Zo = 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
  • 9 selectable SMBus addresses
  • Spread spectrum compatible
  • 6mm × 6mm dual-row 80-GQFN
Find Other Products in Processor Clock Buffers
9QXL2001C - Block Diagram
9QXL2001C - Pin Assignment
9QXL2001C - Block Diagram
9QXL2001C - Pin Assignment

Description

The 9QXL2001C is a 20-output very-low additive phase jitter fanout buffer for PCIe Gen1 to Gen6 applications. The 9QXL2001C provides two methods to control output enables; standard OE# pins and SMBus enable bits, and a simple 3-wire serial interface (side-band interface) that is independent of the SMBus. The side-band interface is enabled via a hardware strap and operates simultaneously with the OE# pins and SMBus enable bits. It offers integrated terminations for 85Ω transmission lines.

Parameters

Attributes Value
Chipset Manufacturer Intel
Clock Spec. Enhanced DB2000QL
Diff. Outputs 20
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 8
Output Freq Range (MHz) 1 - 400
Diff. Inputs 1
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 720
Advanced Features Multiple SMBus addresses, Side Band interface
App Jitter Compliance 25G EDR, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, DB2000Q, QPI, UPI, PCIe Gen6
Package Area (mm²) 81

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 6.0 x 6.0 x 0.85 80 0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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