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9FGV1001

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Programmable PhiClock Generator

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9FGV1001C-9FGV1005C Datasheet

Overview

The 9FGV1001 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1001 provides four non-spread-spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

9FGV1001C - Pinout
9FGV1001C_9FGV1005C - Block Diagram
9FGV1001C - Pinout
9FGV1001C_9FGV1005C - Block Diagram
  • PCIe Gen 1–5 compliant
  • PCIe Gen 5 Common Clock jitter < 80fs RMS
  • 261fs RMS typical phase jitter at 156.25MHz (12kHz to 20MHz)
  • 4 programmable output pairs plus 2 LVCMOS REF outputs
  • 1 integer output frequency per configuration
  • 1MHz to 325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz to 200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V to 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS, and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – See AN-891
  • 4mm × 4mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software

Documentation

Design & Development

Software Downloads
Type Title Date
Software & Tools - Other
9FGV100x Integer v1.4.2 Timing Commander Personality File
ZIP 3.89 MB
Software & Tools - Software
I2C GUI Tool Software
ZIP 9.27 MB
2 items
9FGV1001 - Evaluation Board (perspective)

EVK9FGV1001

Evaluation
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Evaluation Kit for 9FGV1001 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1001 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...

Featured Documents:
9FGV100x Evaluation Board User Guide

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Videos & Training

PCIe Reference Clock Jitter Budgets

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

Related Resources

 

Video List
PCIe Reference Clock Jitter Budgets
PCIe Data Rates vs Clock Jitter Specs
What Does PCIe Gen5 Say About SRIS?
IDT PhiClock™ PCIe Gen 4 Clock Generators, 9FGV100x Family
PCI Express (PCIe) Clock Overview by IDT
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
PCI Express (PCIe) Clock Generators by IDT
PCI Express (PCIe) Clock Applications Overview
PCI Express Gen 1 to Gen 4/Gen 5 Data Rate Evolution
PCI Express Gen 1 to Gen 4/Gen 5 Clock Specification Evolution
PCI Express Common Clock Jitter Model and Transfer Functions

News & Blog Posts

Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System Blog Post Apr 14, 2022
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 22, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018