Overview
Description
Features
- CMOS or LVDS DDR digital outputs
- Dual-channel14-bit pipelined ADC core
- Duty cycle stabilizer
- Fast OTR detection
- Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine
- gain
- INL ±
- 1 LSB, DNL ±
- 0.5 LSB (typical)
- Input bandwidth, 650 MHz
- Offset binary, 2's complement, gray code
- Power dissipation, 775 mW at 80 Msps
- Power-down and Sleep modes
- Sample rate up to 125 Msps
- SFDR, 90 dBc
- Single 3 V supply
- SNR, 73 dB
- SPI Interface
Comparison
Applications
Documentation
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Type | Title | Date |
Datasheet | PDF 600 KB | |
End Of Life Notice | PDF 528 KB | |
2 items
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Design & Development
Boards & Kits
ADC1412D125F1 demo board; CMOS version; SPI, Regulators and CMOS buffer on board
IDT's dual channel ADC demonstration board is suitable for dynamic performances evaluation from low to high IF configuration with LVCMOS outputs. A Data acquisition board can be used to easily analyze the ADC performances in the design and prototyping phase
ADC1412D125F2 demo board; LVDS version; SPI, Regulators and LVDS outputs on board
IDT's dual channel ADC demonstration board is suitable for dynamic performances evaluation from low to high IF configuration with LVDS DDR outputs. A Data acquisition board can be used to easily analyze the ADC performances in the design and prototyping phase.
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Product Options
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