Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 72 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Power Consumption Typ (mW) | 346 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 109 |
| Advanced Features | Multiple SMBus addresses, HW PLL mode control, SW PLL mode control, Programmable input-to-output skew, SMBus security |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI |
| Architecture | Common, SRIS, SRNS |
| C-C Jitter Max P-P (ps) | 50 |
| Chipset Manufacturer | Intel |
| Chipset Name | C600, Patsburg, Wellsburg, Lewisburg |
| Clock Spec. | DB1200ZL v0.8 Derivative Mux |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 12 |
| Diff. Termination Resistors | 24 |
| Feedback Input | No |
| Function | Multiplexer |
| Input Freq (MHz) | 33 - 150 |
| Input Type | HCSL |
| Inputs (#) | 2 |
| Length (mm) | 10 |
| MOQ | 168 |
| Output Banks (#) | 1 |
| Output Enable (OE) Pins | 12 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.7V |
| Outputs (#) | 12 |
| PLL | Yes |
| Package Area (mm²) | 100 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Product Category | Clock Multiplexers, PCI Express Clocks, Processor Clock Buffers, Zero Delay Buffers |
| Prog. Clock | Yes |
| Prog. Interface | SMBUS |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
Resources for 9ZML1253E
Description
The 9ZML1253E is a second-generation enhanced performance DB1200ZL derivative. The part is a pin-compatible upgrade to the 9ZML1232B while offering a much-improved phase jitter performance. Fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.