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9ZML1253E

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2:12 Low-Power PCIe Clock Mux with SMBus Write Protection

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Features

  • SMBus write lock feature; increases system security
  • 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
  • LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
  • 12 OE# pins; hardware control of each output
  • 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL bandwidths; minimize jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL mode; UPI support
  • 10mm x 10mm 72-VFQFPN package; small board footprint
Find Other Products in Processor Clock Buffers
9ZML1253E - Block Diagram
9ZML1253E - Pinout
9ZML1253E - Block Diagram
9ZML1253E - Pinout

Description

The 9ZML1253E is a second-generation enhanced performance DB1200ZL derivative. The part is a pin-compatible upgrade to the 9ZML1232B while offering a much-improved phase jitter performance. Fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.

Parameters

Attributes Value
Chipset Manufacturer Intel
Clock Spec. DB1200ZL v0.8 Derivative Mux
Diff. Outputs 12
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 12
Output Freq Range (MHz) -
Diff. Inputs 2
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 346, 482
Advanced Features Multiple SMBus addresses, HW PLL mode control, SW PLL mode control, Programmable input-to-output skew, SMBus security
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI
Package Area (mm²) 100

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 10.0 x 10.0 x 1.0 72 0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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