Lead Count (#) | 56 |
Pkg. Type | SSOP |
Pkg. Code | PVG56 |
Pitch (mm) | 0.64 |
Pkg. Dimensions (mm) | 18.4 x 7.5 x 2.3 |
Pb (Lead) Free | Yes |
ECCN (US) | NLR |
HTS (US) | 8542390000 |
Moisture Sensitivity Level (MSL) | 1 |
Pkg. Type | SSOP |
Lead Count (#) | 56 |
Pb (Lead) Free | Yes |
Carrier Type | Tube |
100M Non-SSC Outputs | 1 |
100M SSC Outputs | 7 |
25M Outputs | 1 |
Advanced Features | CPU 100M-400M output pair(s), SRC/DOT96 output pair(s), SRC/SE output pair(s), 14.318M output(s), 48M output(s), Integrated VREG |
App Jitter Compliance | PCIe Gen1, PCIe Gen2 |
C-C Jitter Max P-P (ps) | 85 |
Chipset Manufacturer | Intel |
Clock Spec. | CK505 Derivative |
Core Voltage (V) | 3.3 |
Die Form | No |
Diff. Output Signaling | HCSL |
Diff. Termination Resistors | 0 |
Freq. Accuracy Init. (± PPM) | 100 |
Function | Clock Generator |
Input Freq (MHz) | 14.3182 - 14.3182 |
Input Type | Crystal |
Length (mm) | 18.4 |
MOQ | 104 |
Moisture Sensitivity Level (MSL) | 1 |
Output Freq Range (MHz) | 14.32 - 400 |
Output Skew (ps) | 100 |
Output Voltage (V) | 3.3, 0.7 |
Outputs (#) | 19 |
PCI 33.33M Outputs (#) | 5 |
PCIe Generation | Gen1, Gen2 |
Package Area (mm²) | 138.0 |
Pb Free Category | e3 Sn |
Phase Jitter Max RMS (ps) | 3.100 |
Pitch (mm) | 0.64 |
Pkg. Dimensions (mm) | 18.4 x 7.5 x 2.3 |
Power Consumption Typ (mW) | 650 |
Qty. per Carrier (#) | 26 |
Qty. per Reel (#) | 0 |
Reference Output | Yes |
Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
Spread Spectrum | Yes |
Supply Voltage (V) | 1.05 - 3.3 |
Tape & Reel | No |
Temp. Range | 0 to 70°C |
Thickness (mm) | 2.3 |
Width (mm) | 7.5 |
Xtal Freq (MHz) | 14.32 - 14.32 |
Xtal Inputs (#) | 1 |
56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs.