Features
- Integrated terminations; save 32 resistors compared to standard HCSL outputs
- LP-HCSL outputs; support separate VDDIO rail and 130mW typical power consumption
- 8 OE# pins; hardware control of each output
- 25MHz crystal input; exact synthesis
- 100MHz operation; supports PCIe and SATA applications
- VDDIO; allows outputs to run from lower voltage rail to save power
- OE# pins have 1.5V high input threshold; direct interface to 1.8V to 3.3V systems
- < 130mW power consumption (typical)
- Cycle-to-Cycle jitter < 50ps
- Output-to-Output skew < 100ps
- PCIe Gen 2 phase jitter < 3.0ps RMS
- PCIe Gen 3 phase jitter < 1.0ps RMS
- PCIe Gen 3 SRnS clock phase jitter < 0.7ps RMS
Description
The 9FGL839 is an 8-output differential synthesizer for PCI Express Gen 1, Gen 2, and Gen 3 applications. It has integrated terminations providing direct connection to 100Ω transmission lines and saving 32 resistors compared to standard HCSL outputs. The 9FGL839 supports common, data, and Separate Reference no-Spread (SRnS) PCIe clock architectures.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9FGL839AKILF | Obsolete | N/A | In Stock | VFQFPN | 48# | Tray | 3 | 0 | 490# | Yes | e3 Sn | -40 to 85°C |
| 9FGL839AKILFT | Obsolete | N/A | Out of Stock | VFQFPN | 48# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
| 9FGL839AKLF | Obsolete | N/A | Out of Stock | VFQFPN | 48# | Tray | 3 | 0 | 490# | Yes | e3 Sn | 0 to 70°C |
| 9FGL839AKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 48# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
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Datasheets (1)
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015View More (15)
Application Notes & White Papers (15)
- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
- Product Change NoticePDF 95 KB 7WDXRDKU4E7E-5-59609 Oct 22, 2015
- Product Change NoticePDF 50 KB 7WDXRDKU4E7E-5-59245 Jul 21, 2015View More (6)
Product Notices (PCN, EOL, etc) (6)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.