Features
- Direct connection to 100 ohm transmission lines; saves 12 resistors compared to standard PCIe devices
- 47 mW typical power consumption in PLL mode; minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- Spread spectrum tolerant; allows reduction of EMI
- LP-HCSL differential clock outputs; reduced power and board space
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Outputs blocked until PLL is locked; clean system start-up
- Configuration can be accomplished with strapping pins; SMBus interface not required for device control
- 3.3 V tolerant SMBus interface works with legacy controllers
- Space saving 5x5 mm 40-pin VFQFPN; minimal board space
- 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
Description
The 9DBU0631 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 6 output enables for clock management and 3 selectable SMBus addresses.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 167 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 47 |
| Supply Voltage (V) | 1.05 - 1.5, 1.5 - 1.5 |
| Output Type | LP-HCSL |
| Package Area (mm²) | 25 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Input Freq (MHz) | 30 - 175 |
| Additive Phase Jitter Typ RMS (fs) | 313 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.5 |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DBU0631AKILF | Active | Available | In Stock | VFQFPN | 1ku | $1.85 | 40# | Tray | 3 | 0 | 490# | Yes | e3 Sn | -40 to 85°C | THAILAND | TAIWAN |
| 9DBU0631AKILFT | Active | N/A | Out of Stock | VFQFPN | 1ku | $1.85 | 40# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | THAILAND | TAIWAN |
| 9DBU0631AKLF | Active | Available | Out of Stock | VFQFPN | 1ku | $1.69 | 40# | Tray | 3 | 0 | 490# | Yes | e3 Sn | 0 to 70°C | THAILAND | TAIWAN |
| 9DBU0631AKLFT | Active | N/A | Out of Stock | VFQFPN | 1ku | $1.69 | 40# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C | THAILAND | TAIWAN |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
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A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
IDT (acquired by Renesas) engineer provides a brief tutorial on why zero delay buffers (ZDBs) are offered with two different bandwidths (1 MHz and 3 MHz). The reason has to do with jitter peaking when cascading PLLs.
Presented by Ron Wade, PCI Express timing expert.
An overview of IDT's full-featured PCI Express (PCIe) clock zero-delay buffers and fanout buffers addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
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