Features
- Additive PCIe Gen 6 CC jitter < 18fs RMS (Fanout mode)
- PCIe Gen 6 CC jitter < 100fs RMS (High-BW Zero-Delay Buffer (ZDB) mode)
- 2 Low Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
- Direct connection to 85Ω transmission lines
- Dedicated OE# pin for each output
- Spread spectrum tolerant
- Pin or SMBus configuration
- 3 selectable SMBus addresses
- SMBus interface is not required for device operation
- Easy AC coupling to other logic families, see application note AN-891.
- Space-saving 24-pin 4mm × 4mm VFQFPN
Description
The 9DBL0252 2-output zero-delay/fanout buffer is a 3.3V member of Renesas' full-featured PCIe family. The 9DBL0252 supports PCIe Gen 1 through Gen 6 and both Common and Independent Reference Clock architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 200 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 100 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 16 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 1 - 200 |
| Additive Phase Jitter Typ RMS (fs) | 300 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 4.0 x 4.0 x 0.9 | 24 | 0.5 |
| Part Number | Status | Samples | Longevity | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | App Jitter Compliance | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DBL0252CKILF | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 1ku | $1.16 | 24# | Tray | 1 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 | 0 | 490# | Yes | e3 Sn | -40 to 85°C | TAIWAN | TAIWAN |
| 9DBL0252CKILFT | Active | N/A | 2040 Apr | Out of Stock | VFQFPN | 1ku | $1.16 | 24# | Reel | 1 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | TAIWAN |
| 9DBL0252BKILF | Obsolete | N/A | Out of Stock | VFQFPN | 24# | Tray | 1 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 | 0 | 490# | Yes | e3 Sn | -40 to 85°C | ||||
| 9DBL0252BKILFT | Obsolete | N/A | Out of Stock | VFQFPN | 24# | Reel | 1 | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C |
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- DatasheetPDF 570 KB R31DS0116EU0105 Rev.1.05 Nov 05, 2025
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A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
An overview of IDT's full-featured PCI Express (PCIe) clock zero-delay buffers and fanout buffers addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
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