Features
- Four 0.7V current-mode differential HCSL output pairs
- PCIe Gen 3 jitter < 0.6ps RMS in ZDB mode
- PCIe Gen 4 additive jitter < 0.1ps RMS in fanout mode
- SPS internal receiver bias network keeps the input clock parked when input is floating
- Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
- OE# pins default to controlling outputs
- Supports zero delay buffer mode and fanout mode
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible
- Three selectable SMBus addresses
9DB436 - Block Diagram
Description
The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen 1–3 in zero delay mode and PCIe Gen 1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.
Applications
- Riser cards
- Storage
- Networking
- JBOD
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB436AGILF | Obsolete | N/A | Out of Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | Yes | e3 Sn | -40 to 85°C |
| 9DB436AGILFT | Obsolete | N/A | Out of Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | Yes | e3 Sn | -40 to 85°C |
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- End Of Life NoticePDF 859 KB Mar 24, 2022
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (7)
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- End Of Life NoticePDF 859 KB Mar 24, 2022
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial on why zero delay buffers (ZDBs) are offered with two different bandwidths (1 MHz and 3 MHz). The reason has to do with jitter peaking when cascading PLLs.
Presented by Ron Wade, PCI Express timing expert.
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