Features
- 4- 0.7 V HCSL differential output pairs
- Phase jitter: PCIe Gen1 < 86 ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 50-100 MHz operation in PLL mode
- 50-400 MHz operation in Bypass mode
Description
The 9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the 952601, 954101 or 954201. It provides outputs meeting tight cycle-to-cycle jitter (50 ps) and output-to-output skew (50ps) requirements.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Chipset Name | Input Freq (MHz) | Output Voltage (V) | Package Area (mm²) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB401BFLF | Obsolete | N/A | Out of Stock | SSOP | 28# | Tube | 1 | 0 | 47# | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle | 100 - 200 | 0.8V | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB401BFLFT | Obsolete | N/A | Out of Stock | SSOP | 28# | Reel | 1 | 1500# | 0 | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle | 100 - 200 | 0.8V | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB401BGLF | Obsolete | N/A | Out of Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle | 100 - 200 | 0.8V | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
| 9DB401BGLFT | Obsolete | N/A | Out of Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | Blackford, Clarksboro, Greencreek, Lindenhurst, Twincastle | 100 - 200 | 0.8V | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
| 9DB401CFLF | Obsolete | N/A | Out of Stock | SSOP | 28# | Tube | 1 | 0 | 47# | DB400 | 200 | 3.3V | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB401CFLFT | Obsolete | N/A | Out of Stock | SSOP | 28# | Reel | 1 | 1500# | 0 | DB400 | 200 | 3.3V | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB401CGLF | Obsolete | N/A | In Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | DB400 | 200 | 3.3V | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
| 9DB401CGLFT | Obsolete | N/A | In Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | DB400 | 200 | 3.3V | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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