Features
- 19- 0.7 V HCSL differential output pairs
- Phase jitter: PCIe Gen2 < 3.1 ps rms
- Phase jitter: PCIe Gen1 < 86 ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 8 selectable SMBus addresses for easy system expansion 90-147 MHz operation in PLL mode
- 33-400 MHz operation in Bypass mode
Description
The 9DB1904 is electrically compatible to the Intel DB1900GS Differential Buffer Specification. This buffer provides 19-Output clocks for PCI-Express Gen2 or Intel QPI applications. A differential clock from a CK410B+ main clock generator, such as the 932S421 drives the 9DB1904. The 9DB1904 can provide outputs up to 400 MHz in Bypass Mode.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB1904BKLF | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Tray | 3 | 0 | 168# | Yes | e3 Sn | 0 to 70°C |
| 9DB1904BKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- End Of Life NoticePDF 938 KB Feb 28, 2022
- End Of Life NoticePDF 909 KB Jan 20, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Product Change NoticePDF 103 KB 7WDXRDKU4E7E-5-55965 Aug 18, 2013
- Product Change NoticePDF 148 KB 7WDXRDKU4E7E-5-55894 Jul 29, 2013
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (8)
Application Notes & White Papers (8)
- End Of Life NoticePDF 938 KB Feb 28, 2022
- End Of Life NoticePDF 909 KB Jan 20, 2022
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016View More (12)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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