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Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Description

Low skew, low jitter PLL clock driver. 1 to 10 differential clock distribution (SSTL_18)

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
97U2A877AHLFObsoleteN/AOut of StockCABGA52#CYesTray
97U2A877AHLFTObsoleteN/AOut of StockCABGA52#CYesReel
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