Features
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state
Description
Double the drive of the standard 97U877 device. Low skew, low jitter PLL clock driver. 1 to 5 differential clock distribution (SSTL_18)
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 97U2A845AHLF | Obsolete | N/A | Out of Stock | CABGA | 28# | C | Yes | Tray |
| 97U2A845AHLFT | Obsolete | N/A | Out of Stock | CABGA | 28# | C | Yes | Reel |
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- End Of Life NoticePDF 536 KB 7WDXRDKU4E7E-5-62515 Nov 27, 2017
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- End Of Life NoticePDF 536 KB 7WDXRDKU4E7E-5-62515 Nov 27, 2017
Product Notices (PCN, EOL, etc) (1)
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