Features
- 1 - Differential pair open drain CPU clocks at 2.7V
- 1 - Differential pair push-pull CPU clocks at 2.5V
- 11 - PCI including 1 free running and 1 early at 3.3V
- 1 - 48MHz, at 3.3V fixed
- 1 - 24/48MHz at 3.3V
- 3 - REF at 3.3V, 14.318MHz
- Programmable output frequency
- Programmable output rise/fall time
- Programmable slew and skew control for CPUCLK, PCICLK, AGP, REF, 48MHz, and 24_48MHz
- Real-time system reset output
- Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage
- Watchdog timer technology to reset the system if over-clocking causes malfunction
- Uses an external 14.318MHz crystal
Description
The 94228 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. The 94228 employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output-to-output skew, changing spread spectrum amount, changing group divider ratio, and disabling/enabling individual clocks. This device also has propriety watchdog timer technology which will reset the frequency to a safe setting if the system becomes unstable from over-clocking.
Support Communities
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TCP Client Sample (SDK 3.2.2.0)
Hello, I'm trying to run the TCP client sample and connect my device to a TCP server but it's not working (i used this guide : DA16200 FreeRTOS Example Application Guide "UM-WI-055" ) : I defined the TCP server IP address, and i've set the port number (10192 ...
Apr 30, 2022
Support Communities
