Features
- Low skew, low jitter PLL clock driver
- Max frequency supported = 266MHz (DDR 533)
- I2C for functional and output control
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- 3.3V tolerant CLK_INT input
Description
DDR Zero Delay Clock Buffer
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 93732AFLF | Obsolete | N/A | Out of Stock | SSOP | 28# | C | Yes | Tube |
| 93732AFLFT | Obsolete | N/A | Out of Stock | SSOP | 28# | C | Yes | Reel |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Product Change NoticePDF 148 KB 7WDXRDKU4E7E-5-55894 Jul 29, 2013
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- End Of Life NoticePDF 47 KB 7WDXRDKU4E7E-5-46476 Jul 20, 2008
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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Datasheets (1)
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (8)
Application Notes & White Papers (8)
- Product Change NoticePDF 148 KB 7WDXRDKU4E7E-5-55894 Jul 29, 2013
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- End Of Life NoticePDF 47 KB 7WDXRDKU4E7E-5-46476 Jul 20, 2008
Product Notices (PCN, EOL, etc) (3)
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Support Communities
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Lock down and still upgrade SLG46826
I've read through documentation, and I trying to confirm what I understand at this point. The SLG46826 contains NVM and EEPROM that are reprogrammable (MTP). If I want to lock down my device (specifically the 2k registers and the 2k NVM) such that the image can't be pulled ...
Mar 26, 2022
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