Features
- One differential input reference clock
- Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
- Integrated input termination resistors
- Eight LVPECL outputs
- Selectable clock frequency division of ÷1, ÷2, ÷4, and ÷8
- Maximum input clock frequency: 1000MHz
- LVCMOS interface levels for the control inputs
- Individual output enable/disabled via the I²C interface
- Output skew: <60ps
- Output rise/fall times: 350ps (maximum)
- Low additive phase jitter, RMS: 0.182ps (typical)
- Full 2.5V and 3.3V supply voltages
- Available in a lead-free (RoHS 6) 32-lead VFQFN package
- -40 °C to 85 °C ambient operating temperature
Description
The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase noise clocks. The 8T73S208 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make this device ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by an I²C register. On power-up, all outputs are enabled.
Parameters
| Attributes | Value |
|---|---|
| Function | Buffer, Divider |
| Outputs (#) | 8 |
| Output Type | LVPECL |
| Output Freq Range (MHz) | - , - , - , - |
| Input Type | CML, LVDS, LVPECL |
| Output Banks (#) | 1 |
| Output Voltage (V) | 2.5, 3.3 |
| Output Skew (ps) | 60 |
| Additive Phase Jitter Typ RMS (fs) | 182 |
| Advanced Features | Individual output enable, I2C, Per-bank divider, Universal outputs |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 32 | 0.5 |