Features
- Supports PCI Express Gen 1–5
- Four low-skew, low additive jitter LVPECL output pairs
- Two selectable, differential clock input pairs
- Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz
- LVCMOS interface levels for the control input (input select)
- Output skew: 5ps (typical)
- Propagation delay: 320ps (maximum)
- Low additive phase jitter, RMS
- fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz: 40fs (maximum)
- Maximum device current consumption (IEE): 60mA (maximum)
- Full 3.3V or 2.5V supply voltage
- Available in a lead-free (RoHS 6), 16-VFQFPN package
- -40 °C to 85 °C ambient operating temperature
- Supports case temperature ≤105 °C operations
Description
The 8SLVP1204 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase-noise clock and data signals. The 8SLVP1204 is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1204 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low-skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 85°C (Tc ≤ 105°C) |
| Product Category | Clock Buffers & Drivers, Clock Multiplexers, RF Buffers |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |
Support Communities
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Jitter performance for 8SLVP1204
Could you please capture additive jitter performance for 8SLVP1204 with a 312.5MHz carrier.
Mar 23, 2024
Support Communities
