Features
- Eight independent timing channels
- Jitter output below 150fs RMS (typical)
- Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
- DPLLs/Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
- DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
- Supports up to 8 differential; or 16 single-ended reference clock inputs
- Supports up to 12 differential outputs; or 24 LVCMOS outputs
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring, and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive/non-revertive and other programmable settings
- Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
- Optional XO_DPLL input allows a wider range for XO, TCXO, or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
- Serial processor ports support 1MHz I²C or 50MHz SPI
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I²C EPROM via separate I²C Master Port
Description
The 8A34041 multi-channel Digital PLL/Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion, and timing paths for common communications protocols such as Synchronous Ethernet (SyncE), Optical Transport Network (OTN), and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SerDes running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
Parameters
| Attributes | Value |
|---|---|
| Inputs (#) | 16 |
| Input Type | HCSL, LVDS, LVHSTL, LVPECL, SSTL |
| Product Category | ClockMatrix, Ultra-Low Jitter Clocks (<300 fs RMS), Jitter Attenuators, Programmable Clocks |
| Diff. Outputs | 12 |
| Output Type | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL |
| Output Voltage (V) | 1.2V, 1.5V, 1.8V, 2.5V, 3.3V |
| Input Freq (MHz) | 0.001 - 1000 |
| Phase Jitter Typ RMS (ps) | 0.15 |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Fractional Output Dividers (#) | 8 |
| Core Voltage (V) | 2.5V, 3.3V |
| Output Banks (#) | 8 |
| Xtal Freq (KHz) | 25 - 54 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| CABGA | 10.0 x 10.0 x 1.2 | 144 | 0.8 |
Support Communities
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Ultra-Low Noise Clock Generator ICs
Hi All, I am looking for a low phase noise Clock Generator IC that will be able to lock to a 100 MHz reference and generate harmonics of the reference up to ~500 MHz. I need at least 8 outputs, and most importantly, I need the IC to be able ...
Nov 9, 2024
Support Communities
