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Low Skew, 1-to-11 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer

Package Information

Pkg. Type:TQFP
Pkg. Code:PRG32
Lead Count (#):32
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.8

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)32
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFeedback Input
C-C Jitter Max P-P (ps)250
Core Voltage (V)3.3
Feedback InputYes
Input Freq (MHz)100
Input TypeLVCMOS
Inputs (#)1
Length (mm)7
MOQ1000
Output Banks (#)3
Output Freq Range (MHz)180
Output Skew (ps)50
Output TypeLVCMOS
Output Voltage (V)3.3
Outputs (#)11
Package Area (mm²)49
Period Jitter Max P-P (ps)100
Pitch (mm)0.8
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Pkg. TypeTQFP
Product CategoryZero Delay Buffers
Prog. ClockNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1.4
Width (mm)7

Description

The 87952I-147 is a low voltage, low skew LVCMOS/LVTTL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. With output frequencies up to 180MHz, the 87952I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the 87952I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay". For test and system debug purposes, the nPLL_EN input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. The low impedance LVCMOS/LVTTL outputs of the 87952I- 147 are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.