Features
- Fully integrated PLL
- Five differential HSTL output pairs
- Selectable differential CLKx/nCLKx input pairs
- CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
- Output frequency range: 31.25MHz to 700MHz
- Input frequency range: 31.25MHz to 700MHz
- VCO range: 250MHz to 700MHz
- External feedback for "zero delay" clock regeneration
- Cycle-to-cycle jitter: 25ps (maximum)
- Output skew: 25ps (maximum)
- Static phase offset: ±100ps
- 3.3V core, 1.8V output operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- For replacement device use 8725BY-01LF
Description
The 8624 is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8624 has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 700MHz. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Product Change NoticePDF 472 KB 7WDXRDKU4E7E-5-55182 Mar 31, 2013
- End Of Life NoticePDF 541 KB 7WDXRDKU4E7E-5-57906 Nov 12, 2014
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014View More (11)
Application Notes & White Papers (11)
- End Of Life NoticePDF 541 KB 7WDXRDKU4E7E-5-57906 Nov 12, 2014
- Product Change NoticePDF 36 KB 7WDXRDKU4E7E-5-56946 Feb 16, 2014
- Product Change NoticePDF 472 KB 7WDXRDKU4E7E-5-55182 Mar 31, 2013
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